IDT79R4700-133DP IDT, Integrated Device Technology Inc, IDT79R4700-133DP Datasheet - Page 12

• Manufacturer Part Number: IDT79R4700-133DP
• Description: IC MPU 64BIT 5V 133MHZ 208-QFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT79R4700-133DP

• Processor Type: RISC 64-Bit
• Speed: 133MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79R4700-133DP

Absolute Maximum Ratings
IDT79R4700
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
V
V
Interrupt Interface
Int*(5:0)
NMI*
Initialization Interface
V
ColdReset*
Reset*
ModeClock
ModeIn
Pin Name
CC
SS
CCO
V
T
T
T
I
I
Symbol
IN
OUT
1.
2.
3.
P
P
TERM
C
BIAS
STG
V
When V
Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.
k
IN
minimum = -2.0V for pulse width less than 15ns. V
IN
< 0.0V or V
Terminal Voltage with respect to GND
Operating Temperature (case)
Case Temperature Under Bias
Storage Temperature
DC Input Current
DC Output Current
Type
O
I
I
I
I
I
I
I
I
IN
>V
Quiet V
Quiet V
Quiet V
Quiet V
Interrupt
Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register.
Non-maskable interrupt
Non-maskable interrupt, ORed with bit 6 of the interrupt register.
V
When asserted, this signal indicates to the R4700 that the power supply has been above the Vcc minimum
for more than 100 milliseconds and will remain stable. The assertion of V
boot-time-mode-control serial stream.
Cold reset
This signal must be asserted for a power on reset or a cold reset. The clocks SClock, TClock, and RClock
begin to cycle and are synchronized with the de-assertion edge of ColdReset. ColdReset must be de-
asserted synchronously with MasterOut.
Reset
This signal must be asserted for any reset sequence. It may be asserted synchronously or asynchronously
for a cold reset, or synchronously to initiate a warm reset. Reset must be de-asserted synchronously with
MasterOut.
Boot-mode clock
Serial boot-mode data clock output at the system clock frequency divided by two hundred fifty-six.
Boot-mode data in
Serial boot-mode data input.
CC
CC
Rating
.
is OK
CC
SS
SS
CC
for PLL
for the internal phase locked loop.
for the internal phase locked loop.
for PLL
IN
should not exceed V
0 to +85
–55 to +125
–55 to +125
20
50
2
–0.5
12 of 25
Commercial
1
3.3V±5%
to +4.6
RV4700
Description
CC
+0.5V.
0 to +85
–55 to +125
–55 to +125
20
50
–0.5
2
3
1
Commercial
to +7.0
5.0V±5%
CCO
R4700
k initiates the reading of the
V
°C
°C
°C
mA
mA
Unit
December 5, 2008