IDT79RC32V334-150BB IDT, Integrated Device Technology Inc, IDT79RC32V334-150BB Datasheet - Page 14

• Manufacturer Part Number: IDT79RC32V334-150BB
• Description: IC PROC 32BIT CORE 150MHZ 256BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32V334-150BB

• Processor Type: RISC 32-Bit
• Speed: 150MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Family Name: RC32300
• Device Core: MIPS-II
• Device Core Size: 32b
• Frequency (max): 150MHz
• Instruction Set Architecture: MIPS-II
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 79RC32V334-150BB

Clock Parameters — RC32334
Reset Specification
IDT 79RC32334—Rev. Y
(Ta = 0°C to +70°C Commercial, Ta = -40°C to +85°C Industrial, V
cpu_masterclock HIGH
cpu_masterclock LOW
cpu_masterclock period
cpu_masterclock Rise & Fall Time
cpu_masterclock Jitter
pci_clk Rise & Fall Time
pci_clk Period
jtag_tck Rise & Fall Time
ejtag_dck period
jtag_tck clock period
ejtag_dclk High, Low Time
ejtag_dclk Rise, Fall Time
output_clk
cpu_coldreset_n
Asserted during power-up
cpu_coldreset_n Rise Time
1.
2.
3.
RC32334 device. Refer to the RC3233x Device Errata for more information.
cpu_masterclock frequency should never be below pci_clk frequency if PCI interface is used.
Rise and fall times are measured between 10% and 90%
Output_clk should not be used in a system. Only the cpu_masterclock or its derivative must be used to drive all the subsystems with designs based on the
Parameter
3
1
1
VCC
cpu_masterclk
(MClk)
cpu_coldreset_n
modebit[9:0]
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Tdo21
t
MCP
MCHIGH
MCLOW
MCRise,
JITTER
PCRise,
PCP
JCRise,
DCK,
TCK,
DCK High,
DCK Low,
DCK Rise,
DCK Fall,
CRRise
Symbol
t
t
3
11
Figure 3 Mode Configuration Interface Cold Reset Sequence
t
t
t
JCFall
PCFall
MCFall
t
t
t
10
t
10
9
9
Transition ≤ 2ns
Transition ≤ 2ns
—
—
—
PCI 2.2
—
power-on sequence
Test Conditions
Table 5 Clock Parameters - RC32334
>= 110 ms
14 of 30
cc
I/O = +3.3V±5%,V
120 ms
Min
100
N/A
120
20
15
10
RC32334
—
—
—
—
—
—
8
8
4
100MHz
+ 250
Max
66.6
N/A
1.6
—
—
—
—
—
—
—
cc
3
5
1
5
>= 10 ms
Core = +3.3V±5%)
6.75
6.75
Min
100
N/A
120
RC32334
15
—
—
—
15
—
10
—
—
4
133MHz
t
CRRise
+ 250
Max
66.6
N/A
1.6
—
—
—
—
—
—
—
3
5
1
5
13.33
Min
100
N/A
120
15
10
RC32334
—
—
—
—
—
—
6
6
4
150MHz
August 31, 2004
+ 200
Max
66.6
N/A
1.6
—
—
—
—
—
—
—
3
5
1
5
Units
ms
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
—