IDT79RC32V332-133DHG IDT, Integrated Device Technology Inc, IDT79RC32V332-133DHG Datasheet - Page 18

• Manufacturer Part Number: IDT79RC32V332-133DHG
• Description: IC PROC 32BIT CPU 133MHZ 208-QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32V332-133DHG

• Processor Type: RISC 32-Bit
• Speed: 133MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 79RC32V332-133DHG

IDT 79RC32332
Reset
mem_addr[19:17]
mem_addr[19:17]
mem_addr[22:20]
mem_addr[22:20]
Debug Interface
debug_cpu_dma_n,
debug_cpu_ack_n,
debug_cpu_ads_n,
debug_cpu_i_d_n, ejtag_pcst[2:0]
debug_cpu_dma_n,
debug_cpu_ack_n,
debug_cpu_ads_n,
debug_cpu_i_d_n, ejtag_pcst[2:0]
debug_cpu_dma_n,
debug_cpu_ack_n,
debug_cpu_ads_n,
debug_cpu_i_d_n
debug_cpu_dma_n,
debug_cpu_ack_n,
debug_cpu_ads_n,
debug_cpu_i_d_n
JTAG Interface
jtag_tms, jtag_tdi, jtag_trst_n
jtag_tms, jtag_tdi, jtag_trst_n
jtag_tdo
EJTAG Interface
ejtag_tms, ejtag_debugboot
ejtag_tms, ejtag_debugboot
jtag_tdo Output Delay Time
jtag_tdi Input Setup Time
jtag_tdi Input Hold Time
jtag_trst_n Low Time
jtag_trst_n Removal Time
ejtag_tpc Output Delay Time
ejtag_pcst Output Delay Time
1.
2.
3.
4.
At all pipeline frequencies.
Guaranteed by design.
This PCI interface conforms to the PCI Local Bus Specification, Rev 2.2 at 33MHz.
pci_rst_n is tested per PCI 2.2 as an asynchronous signal.
Signal
Tsu10
Thld10
Tsu22
Thld22
Tsu20
Thld20
Tdo20
Tdoh20
t
t
t
t
t
t
t
t
t
t
t
t
TDODO,
TDIS,
TDIH,
TRSTLow,
TRSTR,
TPCDO,
PCSTDO,
Symbol
5
6
4
5
6
t
t
5
6
t
t
t
13
8
4
t
t
7
12
Table 6 AC Timing Characteristics - RC32332 (Part 4 of 4)
cpu_coldreset_n rising
cpu_coldreset_n rising
cpu_masterclk rising
cpu_masterclk rising
cpu_coldreset_n rising
cpu_coldreset_n rising
cpu_masterclk rising
cpu_masterclk rising
jtag_tck rising
jtag_tck rising
jtag_tck falling
jtag_tclk rising
jtag_clk rising
jtag_tck falling
jtag_tck rising
jtag_tck rising
—
jtag_tck rising
ejtag_dclk rising
ejtag_dclk rising
Reference
Edge
18 of 30
100MHz
Min
100
10
10
10
10
—
—
—
-1
-1
1
9
1
1
1
4
2
4
2
3
Max
15
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
3
3
1
133MHz
Min
100
10
10
10
10
—
—
—
-1
-1
1
7
1
1
1
4
2
4
2
3
Max
12
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
3
3
1
150MHz
Min
100
10
10
10
10
—
—
—
-1
-1
1
6
1
1
1
4
2
4
2
3
Max
—
—
—
—
—
—
10
—
—
—
10
—
—
—
—
—
—
6
3
3
1
Units
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chapter 19,
Figures 19.8 and
19.9
Chapter 19,
Figure 19.9 and
Chapter 9,
Figure 9.2
See Figure 4
below.
See Figure 4
below.
User Manual
Reference
May 4, 2004
Diagram
Timing