IDT79RC32V332-100DH IDT, Integrated Device Technology Inc, IDT79RC32V332-100DH Datasheet - Page 9

• Manufacturer Part Number: IDT79RC32V332-100DH
• Description: IC PROC 32BIT CPU 100MHZ 208-QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32V332-100DH

• Processor Type: RISC 32-Bit
• Speed: 100MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC32V332-100DH

IDT 79RC32332
spi_ss_n
CPU Core Specific Signals
cpu_nmi_n
cpu_masterclk
cpu_int_n[1:0]
cpu_coldreset_n
cpu_dt_r_n
JTAG Interface Signals
jtag_tck
jtag_tdi,
ejtag_dint_n
jtag_tdo,
ejtag_tpc
jtag_tms
jtag_trst_n
ejtag_dclk
Name
Output
Output
Output
Type
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Status
Reset
State
H
Z
Z
Z
L
L
Capability
Strength
Drive
High
Low
—
—
—
—
—
—
—
—
—
—
SPI Chip Select
Output pin selecting the serial protocol device as opposed to the PCI satellite mode EEPROM device.
Alternate function: PIO[4]. Defaults to the output direction at reset time.
CPU Non-Maskable Interrupt Requires an external pull-up.
This interrupt input is active low to the CPU.
CPU Master System Clock
Provides the basic system clock.
CPU Interrupt Requires an external pull-up.
These interrupt inputs are active low to the CPU.
CPU Cold Reset
This active-low signal is asserted to the RC32332 after
Reset initialization vectors for the RC32332 are latched by cold reset.
CPU Direction Transmit/Receive
This active-low signal controls the DT/R pin of an optional FCT245 transceiver bank. It is asserted during
read operations.
1st Alternate function: mem_245_dt_r_n.
2nd Alternate function: sdram_245_dt_r_n.
JTAG Test Clock Requires an external pull-down.
An input test clock used to shift into or out of the Boundary-Scan register cells. jtag_tck is independent of
the system and the processor clock with nominal 50% duty cycle.
JTAG Test Data In Requires an external pull-up.
On the rising edge of jtag_tck, serial input data are shifted into either the Instruction or Data register,
depending on the TAP controller state. During Real Mode, this input is used as an interrupt line to stop the
debug unit from Real Time mode and return the debug unit back to Run Time Mode (standard JTAG).
This pin is also used as the ejtag_dint_n signal in the EJTAG mode.
JTAG Test Data Out
The jtag_tdo is serial data shifted out from instruction or data register on the falling edge of jtag_tck.
When no data is shifted out, the jtag_tdo is tri-stated. During Real Time Mode, this signal provides a non-
sequential program counter at the processor clock or at a division of processor clock. This pin is also
used as the ejtag_tpc signal in the EJTAG mode.
JTAG Test Mode Select Requires an external pull-up.
The logic signal received at the jtag_tms input is decoded by the TAP controller to control test operation.
jtag_tms is sampled on the rising edge of the jtag_tck.
JTAG Test Reset
When neither JTAG nor EJTAG are being used, jtag_trst_n must be driven low (pulled down) or the
jtag_tms/ejtag_tms signals must be pulled up and jtag_clk actively clocked.
EJTAG Test Clock
Processor Clock. During Real Time Mode, this signal is used to capture address and data from the
ejtag_tpc signal at the processor clock speed or any division of the internal pipeline.
Table 1 Pin Descriptions (Part 5 of 6)
9 of 30
Description
V
cc
becomes valid on the initial power-up. The
May 4, 2004