IDT79RC32V364-100DA IDT, Integrated Device Technology Inc, IDT79RC32V364-100DA Datasheet - Page 8

• Manufacturer Part Number: IDT79RC32V364-100DA
• Description: IC MPU 32BIT EMB 100MHZ 144-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT79RC32V364-100DA

• Processor Type: RISC 32-Bit
• Speed: 100MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC32V364-100DA

79RC32364™
Retry*
Initialization Interface
ColdReset*
Reset*
DMA Interface
BusReq*
BusGnt*
Interrupt Interface
NMI*
Int*(5:0)
Debug Emulator Interface
TCK
TDI/DINT*
TDO/TPC
TMS
TRST*
DCLK
Pin
I
I
I
I
I
I/O
I
I
I
O
I
I
O
Type
Retry
Indicates that the current bus cycle must be terminated. Retry* is ignored after acceptance of the first data during a read cycle. Dur-
ing a write, Retry* is recognized in all data cycles.
ColdReset
This active-low signal is used for power-on reset.
Reset
This active-low signal is used for both power-on and warm reset.
Bus Request
This active-low signal is an input to the processor that is used to request mastership of the external interface bus. Mastership is
granted according to the assertion of this input, taken back based on its negation.
Bus Grant/ModeBit(5)
This active-low signal is an output from the processor and is used to indicate that the CPU has relinquished mastership of the exter-
nal interface bus. BusGnt* goes low initially for at least 2 clocks to indicate that the CPU has relinquished mastership of the external
interface bus. After going low, BusGnt* returns high, either when the CPU makes an internal request for the bus or after BusReq* is
de-asserted.During the power-on reset (Cold Reset), BusGnt* is an input, ModeBit(5).
Non-Maskable Interrupt
NMI is falling edge sensitive and an asynchronous signal.
Interrupt/ModeBit(9:6)
These interrupt inputs are active low to the CPU. During power-on, Int*(3:0) serves as ModeBit(9:6).
Testclock
An input test clock, used to shift into or out of the Boundary-Scan register cells. TCK is independent of the system and the processor
clock with nominal 50% duty cycle.
TDI/DINT*
On the rising edge of TCK, serial input data are shifted into either the Instruction or Data register, depending on the TAP controller
state. During Real Mode, this input is used as an interrupt line to stop the debug unit from Real Time mode and return the debug unit
back to Run Time Mode (standard JTAG). Requires an external pull-up on the board.
TDO/TPC
The TDO is serial data shifted out from instruction or data register on the falling edge of TCK. When no data is shifted out, the TDO
is tri-stated. During Real Time Mode, this signal provides a non-sequential program counter at the processor clock or at a division of
processor clock.
TMS
The logic signal received at the TMS input is decoded by the TAP controller to control test operation. TMS is sampled on the rising
edge of the TCK. Requires an external pull-up on the board.
TRST*
The TRST* pin is an active-low signal for asynchronous reset of the debug unit, independent of the processor logic. Requires an
external pull-down on the board.
DCLK
Processor Clock. During Real Time Mode, this signal is used to capture address and data from the TDO signal at the processor clock
speed or any division of the internal pipeline.
*Notice: The information in this document is subject to change without notice
Table 3 System Interface Pin Descriptions (Page 3 of 4)
8 of 21
Description
June 20, 2000