IDT79RV4640-133DU IDT, Integrated Device Technology Inc, IDT79RV4640-133DU Datasheet
IDT79RV4640-133DU
Specifications of IDT79RV4640-133DU
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IDT79RV4640-133DU Summary of contents
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Features ◆ High-performance embedded 64-bit microprocessor – 64-bit integer operations – 64-bit registers – Based on the MIPS RISC Architecture – 100MHz, 133MHz, 150MHz, 180MHz, 200MHz and 267MHz operating frequencies – 32-bit bus interface brings 64-bit power to 32-bit system ...
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IDT79RC4640™ Description The IDT79RC4640 is a low-cost member of the Integrated Device Technology, Inc. RC4000 family, targeted to a variety of performance- hungry embedded applications. The RC4640 continues the RC4000 tradition of high-performance through high-speed pipelines, high-band- width caches and ...
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IDT79RC4640™ The MIPS-III architecture defines that the results of a multiply or divide operation are placed in the HI and LO registers. The values can then be transferred to the general purpose register file using the MFHI/ MFLO instructions. The ...
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IDT79RC4640™ System Control Coprocessor (CP0) The system control coprocessor in the MIPS architecture is respon- sible for the virtual to physical address translation and cache protocols, the exception control system, and the diagnostics capability of the processor. In the MIPS ...
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IDT79RC4640™ address is “in bounds”, the value of the corresponding “base” register is added to the virtual address to form the physical address for that refer- ence. If the address is not within bounds, an exception is signalled. This facility ...
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IDT79RC4640™ tents will be updated, and the cache line marked for later write- back. If the cache lookup misses, the target line is first brought into the cache before the cache is updated. ◆ Write-through with write allocate. Loads and ...
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IDT79RC4640™ Boot-Time Options ExtRqst* and Release* are used to transfer control of the SysAD and SysCmd buses between the processor and an external device. When an external device needs to control the interface, it asserts ExtRqst*. The RC4640 responds by ...
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IDT79RC4640™ If the conditions are not correct when the WAIT instruction finishes the W pipe-stage (i.e. the SysAd bus is not idle), the WAIT is treated as a NOP. Once the CPU is in Standby Mode, any interrupt, including the ...
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IDT79RC4640™ Data Sheet Revision History Changes to version dated December 1995: Features: – Added 32-bit bus interface info – Deleted items from low-power operation descriptions. Hardware Overview: – Added detailed descriptions of features. – Changed Boot Time Mode Stream table ...
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IDT79RC4640™ Mode bit Description 0 Reserved (must be zero) 4s:1 Writeback data rate: 32-bit 0 → Ω 1 → WWx 2 → WWxx 3 → WxWx 4 → WWxxx 5 → WWxxxx 6 → WxxWxx 7 → WWxxxxxx 8 → ...
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IDT79RC4640™ Pin Description The following is a list of interface, interrupt, and miscellaneous pins available on the RC4640. Pin names ending with an asterisk (*) identify pins that are active when low. Pin Type Name System Bus Interface ExtRqst* Input ...
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IDT79RC4640™ Pin Type Name ColdReset* Input Cold reset This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted synchronously with MasterClock. Reset* Input Reset This signal must be asserted for any reset ...
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IDT79RC4640™ DC Electrical Characteristics — Commercial Temperature Range—R4640 ± 0°C to +85° CASE Parameter Minimum V — — 2. –0. ...
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IDT79RC4640™ AC Electrical Characteristics — Commercial Temperature Range—R4640 =5.0V ± 5 -0°C to +85°C) CC CASE Clock Parameters—R4640 Parameter Pipeline clock frequency MasterClock HIGH MasterClock LOW 1 MasterClock Frequency MasterClock Period Clock Jitter for MasterClock MasterClock Rise ...
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IDT79RC4640™ Boot-time Interface Parameters—R4640 =5.0V ± 5 0°C to +85°C) CC CASE Parameter Symbol Mode Data Setup t DS Mode Data Hold t DH Capacitive Load Deration—R4650 Parameter Load Derate DC Electrical Characteristics — Commercial / Industrial ...
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IDT79RC4640™ Power Consumption—RV4640 Parameter Typical System Condition 133/67MHz I standby — CC — active, 400 mA 64-bit bus 450 mA option 500 mA 1. Typical integer instruction mix and cache miss rates, Vcc = 3.3V 25×C. 2. These ...
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IDT79RC4640™ AC Electrical Characteristics — Commercial/Industrial Temperature Range—RV4640 =3.3V ± 5%; Commercial CASE Clock Parameters—RV4640 Note: Operation of the RC4650 is only guaranteed with the Phase Lock Loop enabled. Parameter Pipeline clock Frequency MasterClock HIGH MasterClock LOW ...
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IDT79RC4640™ Note: Timings are measured from 1.5V of the clock to 1.5V of the signal. Parameter 1 Data Output Data Output Hold Input Data Setup Input Data Hold 1. Capacitive load for all output timings is 50pF. 2. 50pf loading ...
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IDT79RC4640™ Timing Characteristics—RV4640 Cycle MasterClock SysAD,SysCmd Driven SysADC SysAD,SysCmd Received SysADC Control Signal CPU driven ValidOut* Release* Control Signal CPU received RdRdy* WrRdy* ExtRqst* ValidIn* NMI* Int*(5: active low signal MCkHigh t MCkLow D D ...
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IDT79RC4640™ Mode Configuration Interface Reset Sequence Vcc MasterClock (MClk) VCCOK ModeClock ModeIn ColdReset* Reset* Vcc Master Clock (MClk) TDS VCCOK ModeClock ModeIn TDS ColdReset* TDS Reset* Vcc Master Clock (MClk) VCCOK ModeClock ModeIn ColdReset* Reset* TDS > 100ms 256 MClk ...
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IDT79RC4640™ Physical Specifications - 128-Pin PQFP SYMBOLS MIN A 3.50 A1 .25 A2 3.17 b .30 C .13 D/E 31.00 D1/E1 27. .68 PIN 1 ID ...
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IDT79RC4640™ RC4640 Package Pin-Out N.C. pins should be left floating for maximum flexibility as well as for compatibility with future designs. An asterisk (*) identifies a pin that is active when low. Pin Function 1 N. SysCmd2 34 ...
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IDT79RC4640™ Ordering Information 79 YY XXXX Device Operating Type Voltage Valid Combinations 79R4640 - 100, 133MHz - DZ 79RV4640 - 133, 150, 180, 200, 267MHz - DU 79RV4640 - 133MHz - DUG 79RV4640 - 133, 150, 180, 200MHz - DUI ...