MPC8308CVMAFD Freescale Semiconductor, MPC8308CVMAFD Datasheet - Page 77

• Manufacturer Part Number: MPC8308CVMAFD
• Description: MPU POWERQUICC II PRO 473MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8308CVMAFD

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 333MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 473-MAPBGA
• Product: Network Processor
• Data Rate: 256 bps
• Frequency: 333 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 5 uA
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Interface: I2C, JTAG, SPI
• Mounting Style: SMD/SMT
• Core Size: 32 Bit
• Cpu Speed: 333MHz
• Digital Ic Case Style: MAPBGA
• No. Of Pins: 473
• Operating Temperature Range: -40°C To +105°C
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.1
The primary clock input (SYS_CLK_IN) frequency is multiplied up by the system phase-locked loop
(PLL) and the clock unit to create three major clock domains:
The csb_clk frequency is derived as follows:
The csb_clk serves as the clock input to the e300 core. A second PLL inside the core multiplies up the
csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers
are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL), which is
loaded at power-on reset or by one of the hard-coded reset options. For more information, see the Reset
Clock Configuration chapter in the MPC8308 PowerQUICC II Pro Processor Reference Manual.
The DDR SDRAM memory controller will operate with a frequency equal to twice the frequency of
csb_clk. Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR
clock divider (÷2) to create the differential DDR memory bus clock outputs (MCK and MCK). However,
the data rate is the same frequency as ddr_clk.
The local bus memory controller will operate with a frequency equal to the frequency of csb_clk. Note that
lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the
external local bus clock outputs (LSYNC_OUT and LCLK0:2). The LBC clock divider ratio is controlled
by LCCR[CLKDIV]. For more information, see the Reset Clock Configuration chapter in the MPC8308
PowerQUICC II Pro Processor Reference Manual.
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. These units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset.
frequency. For more information, see Reset Clock Configuration chapter in the MPC8308 PowerQUICC
II Pro Processor Reference Manual.
Freescale Semiconductor
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•
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The coherent system bus clock (csb_clk)
The internal clock for the DDR controller (ddr_clk)
The internal clock for the local bus interface unit (lbc_clk)
csb_clk = [SYS_CLK_IN] × SPMF
System Clock Domains
The clock ratios of these units must be set before they are accessed.
eTSEC1,eTSEC2
I
DMA complex
PCIEXP
eSDHC
USB
2
C
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 2
Unit
Table 54. Configurable Clock Units
Default Frequency
Table 54
csb_clk/3
csb_clk
csb_clk
csb_clk
csb_clk
csb_clk
NOTE
specifies which units have a configurable clock
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk,csb_clk /2, csb_clk /3
Off, csb_clk,csb_clk/2,csb_clk/3
Off, csb_clk , csb_clk /2, csb_clk /3
Off , csb_clk, csb_clk/2, csb_clk/3
Off , csb_clk, csb_clk/2, csb_clk/3
Options
Clocking
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