MPC8540PX667LB Freescale Semiconductor, MPC8540PX667LB Datasheet - Page 8

• Manufacturer Part Number: MPC8540PX667LB
• Description: IC MPU 32BIT 667MHZ 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8540PX667LB

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• For Use With: MPC8548CDS - DEV TOOLS CDS FOR 8548MPC8540ADS-BGA - BOARD APPLICATION DEV 8540CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

MPC8540 Architecture Overview
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L1 cache structure
— 32-Kbyte, 32-byte line, eight-way set-associative instruction cache
— 32-Kbyte, 32-byte line, eight-way set-associative data cache
— 1.5-cycle cache array access, 3-cycle load-to-use latency
— Pseudo-LRU replacement algorithm
— Copy-back data cache
Dual-dispatch superscalar
Precise exception handling
Seven-stage pipeline control
Instruction unit
— Twelve-entry instruction queue
— Full hardware detection of interlocks
— Dispatch up to two instructions per cycle
— Dispatch serialization control
— Register dependency resolution and renaming
Branch unit (BU)
— Dynamic branch prediction
— Two-entry branch instruction queue (BIQ)
— Executes all branch and CR logical instruction
Completion unit
— As many as 14 instructions allowed in 14-entry completion queue
— In-order retirement of up to two instructions per cycle
— Completion and refetch serialization control
— Synchronization for all instruction flow changes—interrupts and mispredicted branches
Two simple execution units that perform the following:
— Single-cycle add and subtract
— Single-cycle shift and rotate
— Single-cycle logical operations
— Supports integer signal processing operations
The SPE APU and SPFP APU functionality will be implemented in the MPC8540,
the MPC8560 and in their derivatives (that is, in all PowerQUICC III devices).
However, these instructions will not be supported in devices subsequent to
PowerQUICC III. Freescale Semiconductor strongly recommends that use of these
instructions be confined to libraries and device drivers. Customer software that
uses SPE or SPFP APU instructions at the assembly level or that uses SPE
intrinsics will require rewriting for upward compatibility with next-generation
PowerQUICC devices.
Freescale offers a lib_moto_e500 library that uses SPE and SPFP APU
instructions. Freescale will also provide future libraries to support next generation
PowerQUICC devices.
MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1
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Freescale Semiconductor