MPC8540PX667LB Freescale Semiconductor, MPC8540PX667LB Datasheet - Page 2

• Manufacturer Part Number: MPC8540PX667LB
• Description: IC MPU 32BIT 667MHZ 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8540PX667LB

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• For Use With: MPC8548CDS - DEV TOOLS CDS FOR 8548MPC8540ADS-BGA - BOARD APPLICATION DEV 8540CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

MPC8540 Overview
Figure 1
2.1 Key Features
The following is an overview of the MPC8540 feature set.
2
•
SDRAM,
SDRAM
GPIO
ROM,
High-performance, 32-bit Book E–enhanced core that implements the PowerPC architecture
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can be locked
— Signal-processing engine (SPE) auxiliary processing unit (APU) provides an extensive instruction set
— The single-precision floating-point (SPFP) APU provides an instruction set for single-precision (32-bit)
— Memory management unit (MMU) especially designed for embedded applications
— Enhanced hardware and software debug support
— Performance monitor facility (similar to but different from the MPC8540 performance monitor
The e500 defines features that are not implemented on the MPC8540. It also generally defines some features
that the MPC8540 implements more specifically. An understanding of these differences can be critical to
ensure proper operation. These differences are summarized in Section 5.14, “MPC8540 Implementation
Details,” in the reference manual.
IRQs
DDR
shows the major functional units in the MPC8540.
Serial
I
MII
entirely or on a per-line basis, with separate locking for instructions and data.
for vector (64-bit) integer, single-precision floating-point, and fractional operations. These instructions
use both the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU.
floating-point instructions.
described in the MPC8540 PowerQUICC III Integrated Host Processor Reference Manual.)
2
C
DDR Memory Controller
Programmable Interrupt
MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1
Local Bus Controller
Ethernet Controller
Controller
10/100 Fast
Interface
DUART
I
2
C
Figure 1. MPC8540 Block Diagram
Coherency
Module
OCeaN
Switch
Fabric
e500
Core Complex
256-Kbyte
L2 Cache/
SRAM
10/100/1Gb
Bus
10/100/1Gb
RapidIO Interface
4-Channel DMA
TSEC
TSEC
PCI/PCI-X Bus
Controller
Interface
32-Kbyte L1
Instruction
Cache
MII, GMII,TBI,
RTBI, RGMII
MII, GMII,TBI,
RTBI, RGMII
e500 Core
Freescale Semiconductor
32-Kbyte
L1 Data
Cache
RapidIO-8
16 Gb/s
PCI-X 64b
133 MHz