MPC8540PX667LB Freescale Semiconductor, MPC8540PX667LB Datasheet - Page 10

• Manufacturer Part Number: MPC8540PX667LB
• Description: IC MPU 32BIT 667MHZ 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8540PX667LB

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• For Use With: MPC8548CDS - DEV TOOLS CDS FOR 8548MPC8540ADS-BGA - BOARD APPLICATION DEV 8540CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

MPC8540 Architecture Overview
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— e500-specific interrupts not defined in Book E architecture
Memory management unit (MMU)
— Data L1 MMU
— Instruction L1 MMU
— Unified L2 MMU
— Software reload for TLBs
— Virtual memory support for as much as 4 Gbytes (2
— Real memory support for as much as 4 Gbytes (2
— Support for big-endian and true little-endian memory on a per-page basis
Power management
— Low power, 1.2-V design
— Dynamic power management on the core minimizes power consumption of functional units, such as
— Core power-saving modes: core-halted and core-stopped
— NAP, DOZE, and SLEEP bits in HID0 that can be used to assert nap, doze, and sleep core output signals
— Internal clock multipliers of 2x, 2.5x, and 3x from bus clock
Testability
— LSSD scan design
— JTAG interface
— ESP support
— ABIST for arrays
— LBIST
Reliability and serviceability
— Internal code parity
— Parity checking on e500 local bus
– Vector offset registers (IVORs) 0–15 as defined in Book E, plus e500-defined IVORs 32–35
– Exception syndrome register (ESR)
– Book E–defined preempting critical interrupt, including critical interrupt status registers (CSRR0
– SPE APU unavailable exception
– Floating-point data exception
– Floating-point round exception
– Performance monitor
– Four-entry, fully-associative TLB array for variable-sized pages
– 64-entry, four-way set-associative TLB for 4-Kbyte pages
– Four-entry, fully-associative TLB array for variable-sized pages
– 64-entry, four-way set-associative TLB for 4-Kbyte pages
– 16-entry, fully-associative TLB array for variable-sized pages
– 256-entry, two-way set-associative TLB for 4-Kbyte pages
execution units, caches, and MMUs, when they are idle.
to initiate power-saving modes at the integrated-device level
and CSRR1) and an rfci instruction
MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1
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) of physical memory
32
) of virtual memory
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