Z9025106PSG Zilog, Z9025106PSG Datasheet - Page 24

• Manufacturer Part Number: Z9025106PSG
• Description: IC 32K 8BIT DTC OTP 42-DIP
• Manufacturer: Zilog

Specifications of Z9025106PSG

• Applications: TV Controller
• Core Processor: Z8
• Program Memory Type: OTP (32 kB)
• Controller Series: Digital Television Controller (DTC)
• Ram Size: 300 x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 27
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 42-DIP (0.600", 15.24mm)
• Processor Series: Z902x
• Core: Z8
• Data Bus Width: 8 bit
• Program Memory Size: 32 KB
• Data Ram Size: 300 B
• Interface Type: I2C
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 27
• Mounting Style: Through Hole
• On-chip Adc: 4 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4
Stop Mode and Halt Mode Operation
4.1
Note:
Stop-Mode Recovery. After this point, the register cannot be modified by any
means, intentional or otherwise.
The WDT is permanently enabled after Reset. To ensure that the WDT is set
properly, use the following instructions as the first two instructions:
The Watch-Dog timer must then be constantly refreshed within the required
timeout by executing the WDT Instruction.
A system reset overrides all other operating conditions and puts the micro-
controller into a known state. To initialize the chipÕs internal logic, the Reset input
must be held Low for at least 5 XTAL clock cycles. The control registers and ports
are reset to default conditions after a POR, a reset from the Reset pin, or a WDT
timeout while in Run Mode and Halt Mode. The control registers and ports are not
reset to their default conditions after Stop Mode Recovery and WDT timeout while
in Stop Mode.
The program counter is loaded with 000Ch. I/O ports and control registers are
configured to their default reset states.
Resetting the microcontroller does not Affect the contents of the general-purpose
registers.
The Watch-Dog Timer (WDT) is a retriggerable, one-shot timer that resets the
microcontroller if it reaches its terminal count. When operating in the Run, Halt or
Stop Modes, a WDT reset is functionally equivalent to a hardware POR reset.
Power-Down Halt-Mode Operation
The Halt Mode suspends instruction execution and turns off the internal CPU
clock. The on-chip oscillator circuit remains active so the internal clock continues
to run and is applied to the counter/timer(s) and interrupt logic.
To enter the Halt Mode, the instruction pipeline must be flushed first to avoid
suspending execution in mid-instruction. To do this, the application program must
DI
WDT
Executing the WDT instruction affects the Z (zero), S (sign),
and V (overflow) flags.
32 KB Television Controller with OSD
PS001301-0800
16