Z9025106PSG Zilog, Z9025106PSG Datasheet - Page 11

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Z9025106PSG

Manufacturer Part Number
Z9025106PSG
Description
IC 32K 8BIT DTC OTP 42-DIP
Manufacturer
Zilog
Datasheets

Specifications of Z9025106PSG

Applications
TV Controller
Core Processor
Z8
Program Memory Type
OTP (32 kB)
Controller Series
Digital Television Controller (DTC)
Ram Size
300 x 8
Interface
I²C, 2-Wire Serial
Number Of I /o
27
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
42-DIP (0.600", 15.24mm)
Processor Series
Z902x
Core
Z8
Data Bus Width
8 bit
Program Memory Size
32 KB
Data Ram Size
300 B
Interface Type
I2C
Maximum Clock Frequency
6 MHz
Number Of Programmable I/os
27
Mounting Style
Through Hole
On-chip Adc
4 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Note:
Figure 2
The Z90255 takes full advantage of ZilogÕs Z8 expanded register file space to
offer greater flexibility in creating a user-friendly On-Screen Display (OSD).
Three basic addressing spaces are available: Program memory, Video RAM
(VRAM) and the Register file. The register file is composed of 300 bytes of
general-purpose registers, 16 control and status registers, one I/O port register
and three reserved registers.
PWM10
RESET
XTAL1
XTAL2
PWM6
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
PWM9
PWM11
ADC0
ADC1
ADC2
ADC3
IRIN
P60
P61
P62
P63
P50
P51
P52
P53
P54
P55
P56
PWM 6 can be either a 6-bit or 14-bit output.
Z90255 Block Diagram
PWM 11 & 6
Oscillator
PWM 10
Counter
Counter
Counter
PWM 1
RESET
(14-bit)
Port 5
(6-bit)
Port 6
Timer
Timer
WDT
4-Bit
ADC
IR
to
Microprocessor
Character RAM
18 KB by 7-Bit
Program ROM
ROM or OTP
Program OTP
Register File
240 x 12-Bit
& 10 x 8-Bit
Character
300 Byte
32 KB
Internal
32 KB
Core
or
32 KB Television Controller with OSD
Interface
On-Screen
Display
Port 2
Port 4
I
2
C
PS001301-0800
SCLK0
SDATA0
SCLK1
SDATA1
P20
P22
P23
P24
P25
P26
P27
P40
P41
P42
P43
P44
P45
P46
P47
OSDX1
OSDX2
P21
G
H
V
R
B
V
HLFTN
SYNC
SYNC
BLANK
3

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