PNX1501E/G,557 NXP Semiconductors, PNX1501E/G,557 Datasheet - Page 634
PNX1501E/G,557
Manufacturer Part Number
PNX1501E/G,557
Description
IC MEDIA PROC 266MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1502EG557.pdf
(828 pages)
Specifications of PNX1501E/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.14 V ~ 1.26 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Ram Size
-
Other names
568-1297
935277747557
PNX1501E/G
935277747557
PNX1501E/G
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Table 13: Source Linear
Table 14: Destination Linear
PNX15XX_SER_3
Product data sheet
Bit
Offset 0x04 F40C
31:24
23:16
15:8
7:0
Bit
Offset 0x04 F410
31:24
23:16
15:8
7:0
Symbol
Reserved
Adr[22:16]
Adr[15:8]
Adr[7:0]
Symbol
Reserved
Adr[22:16]
Adr[15:8]
Adr[7:0]
Source Linear
Destination Linear
When Depth is 16, PFormat[3] enables dithering the results of an alpha blend
operation. All alpha blend operations are done with 8 bits of precision for each
component. The components of the source pixels are expanded to 8 bits by
replicating the high-order bits into the low-order bits. The results of the computations
can be thought of as being in fixed point, with 3, 4, 5 or 6 bits of precision to the left of
the decimal point, depending on the component and color format. When dithering is
enabled, a 4x4 dither is applied by adding a constant fraction to each component and
truncating the results to fit in the resulting pixel. The constant fraction is taken from
the following table, based on the X and Y coordinates of the destination pixel.
Table 12: Dithering
This register is used to load the linear source address for a BLT operation.
It must be loaded with a pixel aligned address. Note that loading the SrcXY register
actually causes this register to be loaded with the proper linear pixel address.
This register is interpreted as a byte address, except during a monochrome host to
screen bit BLT, or a 4-bit or 8-bit expand alpha BLT. In the monochrome BLT case,
Adr[4:0] specifies the first valid bit within the first
Adr[4:3] specifies the correct byte and Adr[2:0] specify the correct bit. In the 4-bit
expand case, Adr[3:0] specifies the first valid nibble within the alpha data transferred
by the host. In the 8-bit expand case, Adr[2:0] specifies the first valid byte within the
alpha data transferred by the host. This register is unchanged by drawing operations.
Format
Y mod 4 = 0
Y mod 4 = 1
Y mod 4 = 2
Y mod 4 = 3
Acces
s
R/W
R/W
R/W
Acces
s
R/W
R/W
R/W
Value
-
-
-
Value
0
0
0
X mod 4 = 0
7/8
1/8
5/8
3/8
Rev. 3 — 17 March 2006
Description
Used to load the linear source address for a BLT operation.
Description
Used to load the starting linear pixel address for a vector or the
destination linear address for a BLT operation.
X mod 4 = 1
3/8
5/8
7/8
1/8
DWORD
Chapter 20: 2D Drawing Engine
X mod 4 = 2
1/8
7/8
3/8
5/8
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
transferred by the host.
PNX15xx Series
X mod 4 = 3
5/8
3/8
1/8
7/8
20-18
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