CY7C66113C-PVXC Cypress Semiconductor Corp, CY7C66113C-PVXC Datasheet - Page 17

• Manufacturer Part Number: CY7C66113C-PVXC
• Description: IC MCU 8K USB HUB 4 PORT 56TSSOP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113C-PVXC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• No. Of I/o's: 31
• Eeprom Memory Size: 8KB
• Ram Memory Size: 256Byte
• Cpu Speed: 48MHz
• Digital Ic Case Style: SSOP
• Supply: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 8KB
• Oscillator Type: External, Internal
• Peripherals: DAC
• Rohs Compliant: Yes
• Controller Family/series: (8051) USB
• Embedded Interface Type: HAPI, I2C, USB
• Processor Series: CY7C66xx
• Core: M8
• Data Bus Width: 16 bit
• Data Ram Size: 256 B
• Interface Type: HAPI, I2C, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details
• Other names: 428-1808

GPIO Configuration Port
Every GPIO port is programmed as inputs with internal pull ups, outputs LOW or HIGH, or Hi-Z (floating, the pin is not driven internally).
In addition, the interrupt polarity for each port is programmed. The Port Configuration bits
(Figure 10
GPIO Configuration
As shown in
represents a rising edge interrupt (LOW to HIGH), and a negative
polarity on an input pin represents a falling edge interrupt (HIGH
to LOW).
The GPIO interrupt is generated when all of the following
conditions are met: the Interrupt Enable bit of the associated Port
Interrupt Enable Register is enabled, the GPIO Interrupt Enable
bit of the Global Interrupt Enable Register
the Interrupt Enable Sense (bit 2,
pin of the port sees an event matching the interrupt polarity.
Table 6. GPIO Port Output Control Truth Table and Interrupt Polarity
Q1, Q2, and Q3 discussed here are the transistors referenced in
Figure
■
■
Document Number: 38-08024 Rev. *D
Port Config Bit 1 Port Config Bit 0 Data Register Output Drive Strength Interrupt Enable Bit
Bit #
Bit Name
Read/Write
Reset
Output LOW Mode: The pin’s Data Register is set to ‘0’
Output HIGH Mode: The pin’s Data Register is set to 1 and the
Port Configuration Bits[1:0] is set to ‘10’
Writing ‘0’ to the pin’s Data Register puts the pin in output
LOW mode, regardless of the contents of the Port
Configuration Bits[1:0]. In this mode, Q1 and Q2 are OFF. Q3
is ON. The GPIO pin is driven LOW through Q3.
In this mode, Q1 and Q3 are OFF. Q2 is ON. The GPIO is
pulled up through Q2. The GPIO pin is capable of sourcing
current.
7. The available GPIO drive strength are:
1
1
0
0
through
7
Port 3
Config Bit 1
R/W
0
Table
Figure
6, a positive polarity on an input pin
16) determine the interrupt polarity of the port pins.
1
0
1
0
6
Port 3
Config Bit 0
R/W
0
Figure
28) is set, and the GPIO
(Figure
Figure 12. GPIO Configuration Register
5
Port 2
Config Bit 1
R/W
0
0
1
0
1
0
1
0
1
29) is enabled,
Output LOW
Resistive
Output LOW
Output HIGH
Output LOW
Hi-Z
Output LOW
Hi-Z
4
Port 2
Config Bit 0
R/W
0
The driving state of each GPIO pin is determined by the value
written to the pin’s Data Register
and by its associated Port Configuration bits as shown in the
GPIO Configuration Register
configured on a per port basis, so all pins in a given port are
configured together. The possible port configurations are
detailed in
configured with CMOS outputs, interrupts from that port are
disabled.
During reset, all the bits in the GPIO Configuration Register are
written with ‘0’ to select Hi-Z mode for all GPIO ports as the
default configuration.
■
■
Resistive Mode: The pin’s Data Register is set to 1 and the Port
Configuration Bits[1:0] is set to ‘11’
Hi-Z Mode: The pin’s Data Register is set to1 and Port
Configuration Bits[1:0] is set either ‘00’ or ‘01’
Q2 and Q3 are OFF. Q1 is ON. The GPIO pin is pulled up with
an internal 14 kΩ resistor. In resistive mode, the pin may serve
as an input. Reading the pin’s Data Register returns a logic
HIGH if the pin is not driven LOW by an external source.
Q1, Q2, and Q3 are all OFF. The GPIO pin is not driven
internally. In this mode, the pin may serve as an input.
Reading the Port Data Register returns the actual logic value
on the port pins.
3
Port 1
Config Bit 1
R/W
0
Table
6. As shown in this table, when a GPIO port is
CY7C66013C, CY7C66113C
2
Port 1
Config Bit 0
R/W
0
(Figure
0
1
0
1
0
1
0
1
12) and the Interrupt Enable bit
(Figure
1
Port 0
Config Bit 1
R/W
0
(Figure 8
Disabled
– (Falling Edge)
Disabled
Disabled
Disabled
– (Falling Edge)
Disabled
+ (Rising Edge)
10). These ports are
Interrupt Polarity
through
ADDRESS 0x08
0
Port 0
Config Bit 0
R/W
0
Page 17 of 59
Figure
11)
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