CY7C63723-SC Cypress Semiconductor Corp, CY7C63723-SC Datasheet - Page 34

• Manufacturer Part Number: CY7C63723-SC
• Description: IC MCU 8K LS USB/PS-2 18-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63723-SC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C637xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 10
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1323

The response of the SIE can be summarized as follows:
Table 22-3. Details of Modes for Differing Traffic Conditions
Document #: 38-08022 Rev. *B
1. The SIE will only respond to valid transactions, and will ig-
2. The SIE will generate an interrupt when a valid transaction
3. An incoming Data packet is valid if the count is < Endpoint
4. An IN will be ignored by an OUT configured endpoint and
5. The IN and OUT PID status is updated at the end of a
End Point Mode
3
SETUP Packet
See22-1
See22-1
See 22-1
Disabled
0
NAK IN/OUT
0
0
0
0
Ignore IN/OUT
0
0
STALL IN/OUT
0
0
0
0
Control Write
ACK OUT/NAK IN
1
1
1
1
NAK OUT/Status IN
1
1
1
1
Status IN Only
0
0
0
0
nore non-valid ones.
is completed or when the FIFO is corrupted. FIFO
corruption occurs during an OUT or SETUP transaction to
a valid internal address, that ends with a non-valid CRC.
Size + 2 (includes CRC) and passes all error checking;
visa versa.
transaction.
2
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0 x
1 OUT
1 OUT
1 OUT
1 IN
0 OUT
0 IN
1 OUT
1 OUT
1 OUT
1 IN
1 OUT
1 OUT
1 OUT
1 IN
0 OUT
0 OUT
0 OUT
0 IN
0 OUT
0 OUT
0 OUT
0 IN
Rcved
Token
SETUP
SETUP
SETUP
(if accepting)
Count
<= 10
> 10
x
x
x
> 10
x
x
x
x
x
> 10
x
x
<= 10
> 10
x
x
<= 10
> 10
x
x
<= 10
> 10
x
x
Buffer
data
junk
junk
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
data
junk
junk
UC
UC
UC
UC
UC
UC
UC
UC
UC
FOR
FOR
Dval
valid
x
invalid
x
x
x
invalid
x
x
x
x
x
invalid
x
valid
x
invalid
x
valid
x
invalid
x
valid
x
invalid
x
DTOG
updates
updates
updates
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
updates
updates
updates
UC
UC
UC
UC
UC
UC
UC
UC
UC
DVAL
1
updates
0
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
1
updates
0
UC
UC
UC
UC
UC
UC
UC
UC
UC
updates
COUNT
updates
updates
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
updates
updates
updates
UC
UC
UC
UC
UC
UC
UC
UC
UC
6. The SETUP PID status is updated at the beginning of the
7. The entire Endpoint 0 mode register and the Count register
Data packet phase.
are locked to CPU writes at the end of any transaction to
that endpoint in which an ACK is transferred. These
registers are only unlocked by a CPU read of these
registers, and only if that read happens after the transaction
completes. This represents about a 1-µs window in which
the CPU is locked from register writes to these USB
registers. Normally the firmware should perform a register
read at the beginning of the Endpoint ISRs to unlock and
get the mode register information. The interlock on the
Mode and Count registers ensures that the firmware
recognizes the changes that the SIE might have made
during the previous transaction.
PID
SETUP
1
1
1
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
IN
UC
UC
UC
UC
UC
UC
UC
1
UC
UC
UC
UC
UC
1
UC
UC
UC
1
UC
UC
UC
1
UC
UC
UC
1
OUT
UC
UC
UC
UC
1
UC
UC
UC
UC
UC
1
UC
UC
UC
1
1
1
UC
1
UC
UC
UC
1
UC
UC
UC
ACK
1
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
1
UC
UC
UC
UC
UC
UC
1
UC
UC
UC
1
Set End Point Mode
3
0
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
0
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
NoChange
0
NoChange
NoChange
NoChange
2 1 0 Response
0 0 1 ACK
0 0 1 ACK
0 1 1 STALL
CY7C63722
CY7C63723
CY7C63743
Page 34 of 49
Ignore
Ignore
Ignore
NAK
Ignore
Ignore
NAK
Ignore
Ignore
STALL
Ignore
Ignore
STALL
Ignore
Ignore
NAK
NAK
Ignore
Ignore
TX 0 Byte
Ignore
Ignore
TX 0 Byte
Int
yes
yes
yes
no
yes
no
no
yes
no
no
yes
no
no
yes
yes
yes
yes
yes
yes
no
no
yes
yes
no
no
yes