XC5VLX220T-1FFG1738C Xilinx Inc, XC5VLX220T-1FFG1738C Datasheet - Page 378
XC5VLX220T-1FFG1738C
Manufacturer Part Number
XC5VLX220T-1FFG1738C
Description
IC FPGA VIRTEX-5 220K 1738FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX220T-1FFG1738C
Total Ram Bits
7815168
Number Of Logic Elements/cells
221184
Number Of Labs/clbs
17280
Number Of I /o
680
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1738-BBGA, FCBGA
No. Of Logic Blocks
17280
No. Of Macrocells
220000
Family Type
Virtex-5
No. Of Speed Grades
1
No. Of I/o's
680
Clock Management
DCM, PLL
Core Supply
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX220T-1FFG1738C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX220T-1FFG1738C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
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Chapter 8: Advanced SelectIO Logic Resources
378
Timing Characteristics of 2:1 SDR Serialization
Table 8-11: OSERDES Switching Characteristics (Continued)
In
X-Ref Target - Figure 8-17
Clock Event 1
On the rising edge of CLKDIV, the word AB is driven from the FPGA logic to the D1 and
D2 inputs of the OSERDES (after some propagation delay).
Clock Event 2
On the rising edge of CLKDIV, the word AB is sampled into the OSERDES from the D1 and
D2 inputs.
Clock Event 3
The data bit A appears at OQ one CLK cycle after AB is sampled into the OSERDES. This
latency is consistent with the
CLK cycle.
Combinatorial
T
T
OSCO_OQ
OSCO_TQ
Figure
CLKDIV
CLK
OQ
D1
D2
Event 1
8-17, the timing of a 2:1 SDR data serialization is illustrated.
Figure 8-17: OSERDES Data Flow and Latency in 2:1 SDR Mode
Symbol
Clock
Event 2
Clock
www.xilinx.com
B
A
Table 8-10
Asynchronous Reset to OQ
Asynchronous Reset to TQ
Clock
Event 3
A
listing of a 2:1 SDR mode OSERDES latency of one
C
D
B
C
E
F
Description
D
E
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
F
UG190_8_17_100307
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