XC5VLX220T-1FFG1738C Xilinx Inc, XC5VLX220T-1FFG1738C Datasheet - Page 335
XC5VLX220T-1FFG1738C
Manufacturer Part Number
XC5VLX220T-1FFG1738C
Description
IC FPGA VIRTEX-5 220K 1738FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX220T-1FFG1738C
Total Ram Bits
7815168
Number Of Logic Elements/cells
221184
Number Of Labs/clbs
17280
Number Of I /o
680
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1738-BBGA, FCBGA
No. Of Logic Blocks
17280
No. Of Macrocells
220000
Family Type
Virtex-5
No. Of Speed Grades
1
No. Of I/o's
680
Clock Management
DCM, PLL
Core Supply
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX220T-1FFG1738C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX220T-1FFG1738C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
The timing diagram in
I/O is an output switching to an input using 3-state control. The switching characteristics
shown in the diagram are specified in the Virtex-5 FPGA Data Sheet.
X-Ref Target - Figure 7-12
The activities of the OBUFT pin are controlled by the propagation and state of the
TSCONTROL signal from the ODDR flip-flop. The 3-state control data receipt on the
OBUF and IDDR flip-flop from a PAD are in parallel with each other, depending on the
IDELAY_VALUE setting the final value at the IDDR flip-flop input in response to a clock
edge is valid before or after the pad is driven from the 3-state control. After the 3-state
control propagates through to the PAD and the IODELAY has been switched to an input,
the IDDR setup time is the sole determiner of timing based on the IDELAY_VALUE and
other timing parameters defined in the Xilinx speed specification and represented in the
ISE tools.
Figure 7-12: Relevant Timing Signals to Examine IODELAY Timing when the IOB
TSCONTROL
ODDR CLK
IDDR CLK
PAD
Figure 7-12
ODDR CLK to 3-state
deassertion time.
Switches From an Output to an Input
www.xilinx.com
Previous PAD
Output Value
ODDR CLK to
shows the relevant signal timing for the case when the
IDELAY ready
T
OCKQ
T
IODDO_T
T
IOTP
Input/Output Delay Element (IODELAY)
T
IOPI
function of IDELAY_VALUE)
Pad to IDDR Setup Time is:
(where T
+ T
IODDO_IDATAIN
IODDO_IDATAIN
Input Value
New PAD
+ T
IODELAY_03_082107
is a
IDOCKD
335
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