XC5VLX220T-1FFG1738C Xilinx Inc, XC5VLX220T-1FFG1738C Datasheet - Page 338
XC5VLX220T-1FFG1738C
Manufacturer Part Number
XC5VLX220T-1FFG1738C
Description
IC FPGA VIRTEX-5 220K 1738FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX220T-1FFG1738C
Total Ram Bits
7815168
Number Of Logic Elements/cells
221184
Number Of Labs/clbs
17280
Number Of I /o
680
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1738-BBGA, FCBGA
No. Of Logic Blocks
17280
No. Of Macrocells
220000
Family Type
Virtex-5
No. Of Speed Grades
1
No. Of I/o's
680
Clock Management
DCM, PLL
Core Supply
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Company:
Part Number:
XC5VLX220T-1FFG1738C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC5VLX220T-1FFG1738C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
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Chapter 7: SelectIO Logic Resources
338
IDELAYCTRL Primitive
IDELAYCTRL Ports
Figure 7-15
X-Ref Target - Figure 7-15
RST - Reset
The reset input pin (RST) is an active-High asynchronous reset. IDELAYCTRL must be
reset after configuration (and the REFCLK signal has stabilized) to ensure proper
IODELAY operation. A reset pulse width T
must be reset after configuration.
REFCLK - Reference Clock
The reference clock (REFCLK) provides a time reference to IDELAYCTRL to calibrate all
IODELAY modules in the same region. This clock must be driven by a global clock buffer
(BUFGCTRL). REFCLK must be F
(IDELAYCTRL_REF_PRECISION) to guarantee a specified IODELAY resolution
(T
PLL, or from the DCM, and must be routed on a global clock buffer.
RDY - Ready
The ready (RDY) signal indicates when the IODELAY modules in the specific region are
calibrated. The RDY signal is deasserted if REFCLK is held High or Low for one clock
period or more. If RDY is deasserted Low, the IDELAYCTRL module must be reset. The
implementation tools allow RDY to be unconnected/ignored.
timing relationship between RDY and RST.
IDELAYRESOLUTION
shows the IDELAYCTRL primitive.
). REFCLK can be supplied directly from a user-supplied source, the
Figure 7-15: IDELAYCTRL Primitive
www.xilinx.com
IDELAYCTRL_REF
REFCLK
RST
IDELAYCTRL
IDELAYCTRL_RPW
ug190_7_10_041206
RDY
± the specified ppm tolerance
is required. IDELAYCTRL
Figure 7-16
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
illustrates the
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