XC5VSX50T-1FF1136I Xilinx Inc, XC5VSX50T-1FF1136I Datasheet - Page 362
![IC FPGA VIRTEX-5 50K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX50T-1FF1136I
Manufacturer Part Number
XC5VSX50T-1FF1136I
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX50T-1FF1136I
Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Chapter 8: Advanced SelectIO Logic Resources
362
Guidelines for Expanding the Serial-to-Parallel Converter Bit Width
X-Ref Target - Figure 8-7
1.
2.
3.
4.
5.
Both ISERDES modules must be adjacent master and slave pairs. Both ISERDES
modules must be in NETWORKING mode because width expansion is not available in
MEMORY mode.
Set the SERDES_MODE attribute for the master ISERDES to MASTER and the slave
ISERDES to SLAVE. See
The user must connect the SHIFTIN ports of the SLAVE to the SHIFTOUT ports of the
MASTER.
The SLAVE only uses the ports Q3 to Q6 as an input.
DATA_WIDTH applies to both MASTER and SLAVE in
Data Input
Figure 8-7: Block Diagram of ISERDES Width Expansion
SERDES_MODE=MASTER
D
D
SERDES_MODE=SLAVE
SHIFTOUT1 SHIFTOUT2
www.xilinx.com
SHIFTIN1
SERDES_MODE
ISERDES
ISERDES
(Master)
(Slave)
SHIFTIN2
Attribute.
Q1
Q2
Q3
Q4
Q5
Q6
Q1
Q2
Q3
Q4
Q5
Q6
Figure
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Data_internal [0:5]
Data_internal [6:9]
8-7.
ug190_8_07_100307
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