XC5VSX50T-1FF1136I Xilinx Inc, XC5VSX50T-1FF1136I Datasheet - Page 327
![IC FPGA VIRTEX-5 50K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX50T-1FF1136I
Manufacturer Part Number
XC5VSX50T-1FF1136I
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX50T-1FF1136I
Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
IODELAY Ports
Table 7-7: IODELAY Primitive Ports (Continued)
Data Input from the IOB - IDATAIN
The IDATAIN input is driven by its associated IOB. In IDELAY mode the data can be
driven to either an ILOGIC/ISERDES block, directly into the FPGA fabric, or to both
through the DATAOUT port with a delay set by the IDELAY_VALUE.
Data Input from the FPGA Fabric - ODATAIN
The ODATAIN input is driven by OLOGIC/OSERDES. In ODELAY mode, the ODATAIN
drives the DATAOUT port which is connected to an IOB with a delay set by the
ODELAY_VALUE.
Data Input for IODELAY from the FPGA Fabric - DATAIN
The DATAIN input is directly driven by the FPGA fabric providing a fabric logic accessible
delay line. The data is driven back into the fabric through the DATAOUT port with a delay
set by the IDELAY_VALUE. DATAIN can be locally inverted. The data cannot be driven to
an IOB.
Data Output - DATAOUT
Delayed data from the three data input ports. DATAOUT connects to the fabric (IDELAY
mode), or an IOB (ODELAY mode) or both (bidirectional delay mode). If used in the
bidirectional delay mode, the T port dynamically switches between the IDATAIN and
ODATAIN paths providing an alternating input/output delay based on the direction
indicated by the 3-state signal T from the OLOGIC block.
3-state Input - T
This is the 3-state input control port. For bidirectional operation, the T pin signal also
controls the T pin of the OBUFT.
Clock Input - C
All control inputs to IODELAY primitive (RST, CE, and INC) are synchronous to the clock
input (C). A clock must be connected to this port when IODELAY is configured in variable
mode. C can be locally inverted, and must be supplied by a global or regional clock buffer.
This clock should be connected to the same clock in the SelectIO logic resources (when
using ISERDES and OSERDES, C is connected to CLKDIV).
DATAIN
Name
Port
INC
RST
CE
C
T
Direction
Input
Input
Input
Input
Input
Input
www.xilinx.com
Data input for IODELAY from the FPGA fabric
3-state input control port. This port determines dynamically
if IODELAY is used as IDELAY or ODELAY.
Enable increment/decrement function
Increment/decrement number of tap delays
Reset the IODELAY element to the pre-programmed value
Clock input used in variable mode
Input/Output Delay Element (IODELAY)
Function
327
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