XC5VSX50T-1FF1136I Xilinx Inc, XC5VSX50T-1FF1136I Datasheet - Page 252
![IC FPGA VIRTEX-5 50K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX50T-1FF1136I
Manufacturer Part Number
XC5VSX50T-1FF1136I
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX50T-1FF1136I
Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Chapter 6: SelectIO Resources
252
HSTL Class I
Figure 6-40
Class I.
X-Ref Target - Figure 6-40
Table 6-15
Table 6-15: HSTL Class I DC Voltage Specifications
Notes:
1. V
2. Per EIA/JESD8-6, “The value of V
V
V
V
V
V
V
V
I
I
OH
OL
CCO
REF
TT
IH
IL
OH
OL
the use conditions specified by the user.”
OL
at V
External Termination
DCI
at V
(2)
and V
HSTL_I_DCI
OL
OH
lists the HSTL Class I DC voltage specifications.
HSTL_I
(mA)
shows a sample circuit illustrating a valid termination technique for HSTL
OH
(mA)
for lower drive currents are sample tested.
IOB
IOB
(1)
(1)
Figure 6-40: HSTL Class I Termination
www.xilinx.com
Z 0
Z 0
R P = Z 0 = 50Ω
REF
is to be selected by the user to provide optimum noise margin in
V
TT
V
IOB
CCO
= 0.75V
= 1.5V
2R
2R
V
V
VRP
VRN
CCO
REF
Min
1.40
0.68
–8
IOB
= 2Z 0 = 100Ω
–
–
–
8
V
= 2Z 0 = 100Ω
V
+ 0.1
REF
– 0.4
REF
= 0.75V
= 0.75V
V
CCO
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
1.50
0.75
Typ
HSTL_I_DCI
–
–
–
–
–
–
× 0.5
HSTL_I
+
–
+
–
ug190_6_38_030206
V
REF
Max
1.60
0.90
0.4
–
–
–
–
–
– 0.1
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