XC2V40-5FGG256C Xilinx Inc, XC2V40-5FGG256C Datasheet - Page 83
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XC2V40-5FGG256C
Manufacturer Part Number
XC2V40-5FGG256C
Description
IC FPGA VIRTEX-II 40K 256-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-IIr
Datasheet
1.XC2V250-4FGG256C.pdf
(318 pages)
Specifications of XC2V40-5FGG256C
Number Of Labs/clbs
64
Total Ram Bits
73728
Number Of I /o
88
Number Of Gates
40000
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
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DCM Timing Parameters
All devices are 100% functionally tested. Because of the dif-
ficulty in directly measuring many internal timing parame-
ters, those parameters are derived from benchmark timing
patterns. The following guidelines reflect worst-case values
Operating Frequency Ranges
e
Table 38: Operating Frequency Ranges
DS031-3 (v3.5) November 5, 2007
Product Specification
Notes:
1.
2.
3.
4.
Output Clocks (Low Frequency Mode)
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
Input Clocks (Low Frequency Mode)
CLKIN (using DLL outputs)
CLKIN (using CLKFX outputs)
PSCLK
Output Clocks (High Frequency Mode)
CLK0, CLK180
CLKDV
CLKFX, CLKFX180
Input Clocks (High Frequency Mode)
CLKIN (using DLL outputs)
CLKIN (using CLKFX outputs)
PSCLK
“DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
If both DLL and CLKFX outputs are used, follow the more restrictive specification.
If the CLKIN_DIVIDE_BY_2 attribute of the DCM is used, then double these values.
If the CLKIN_DIVIDE_BY_2 attribute of the DCM is used and CLKIN frequency > 400 MHz, CLKIN duty cycle must be within ±5% (45/55 to 55/45).
Description
R
(1,3,4)
(1,3,4)
(2,3,4)
(2,3,4)
CLKOUT_FREQ_1X_LF_Min
CLKOUT_FREQ_1X_LF_Max
CLKOUT_FREQ_2X_LF_Min
CLKOUT_FREQ_2X_LF_Max
CLKOUT_FREQ_DV_LF_Min
CLKOUT_FREQ_DV_LF_Max
CLKOUT_FREQ_FX_LF_Min
CLKOUT_FREQ_FX_LF_Max
CLKIN_FREQ_DLL_LF_Min
CLKIN_FREQ_DLL_LF_Max
CLKIN_FREQ_FX_LF_Min
CLKIN_FREQ_FX_LF_Max
PSCLK_FREQ_LF_Min
PSCLK_FREQ_LF_Max
CLKOUT_FREQ_1X_HF_Min
CLKOUT_FREQ_1X_HF_Max
CLKOUT_FREQ_DV_HF_Min
CLKOUT_FREQ_DV_HF_Max
CLKOUT_FREQ_FX_HF_Min
CLKOUT_FREQ_FX_HF_Max
CLKIN_FREQ_DLL_HF_Min
CLKIN_FREQ_DLL_HF_Max
CLKIN_FRQ_FX_HF_Min
CLKIN_FRQ_FX_HF_Max
PSCLK_FREQ_HF_Min
PSCLK_FREQ_HF_Max
Symbol
www.xilinx.com
Virtex-II Platform FPGAs: DC and Switching Characteristics
across the recommended operating conditions. All output
jitter and phase specifications are determined through sta-
tistical measurement at the package pins.
Constraint
s
230.00
450.00
150.00
260.00
230.00
260.00
450.00
450.00
300.00
210.00
350.00
450.00
350.00
450.00
24.00
48.00
24.00
24.00
48.00
48.00
50.00
1.50
1.00
0.01
3.00
0.01
-6
Speed Grade
420.00
280.00
210.00
420.00
210.00
420.00
140.00
240.00
210.00
240.00
420.00
320.00
420.00
320.00
24.00
48.00
24.00
24.00
48.00
48.00
50.00
1.50
1.00
0.01
3.00
0.01
-5
180.00
360.00
120.00
210.00
180.00
210.00
360.00
360.00
240.00
210.00
270.00
360.00
270.00
360.00
24.00
48.00
24.00
24.00
48.00
48.00
50.00
1.50
1.00
0.01
3.00
0.01
-4
Module 3 of 4
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
s
35
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