XC2V40-5FGG256C Xilinx Inc, XC2V40-5FGG256C Datasheet - Page 14
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XC2V40-5FGG256C
Manufacturer Part Number
XC2V40-5FGG256C
Description
IC FPGA VIRTEX-II 40K 256-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-IIr
Datasheet
1.XC2V250-4FGG256C.pdf
(318 pages)
Specifications of XC2V40-5FGG256C
Number Of Labs/clbs
64
Total Ram Bits
73728
Number Of I /o
88
Number Of Gates
40000
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
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Some input standards require a user-supplied threshold
voltage (V
configured as V
I/O pins in the bank assume this role.
V
consequently only one V
each bank. However, for correct operation, all V
the bank must be connected to the external reference volt-
age source.
The V
device pinout tables. Within a given package, the number of
V
device. In larger devices, more I/O pins convert to V
pins. Since these are always a superset of the V
used for smaller devices, it is possible to design a PCB that
permits migration to a larger device if necessary.
All V
nected to the V
DS031-2 (v3.5) November 5, 2007
Product Specification
Figure 7: Virtex-II I/O Banks: Top View for Wire-Bond
REF
REF
Figure 8: Virtex-II I/O Banks: Top View for Flip-Chip
REF
pins within a bank are interconnected internally, and
CCO
and V
Packages (CS/CSG, FG/FGG, & BG/BGG)
pins for the largest device anticipated must be con-
REF
and the V
R
CCO
), and certain user-I/O pins are automatically
REF
REF
pins can vary depending on the size of
Packages (FF & BF)
voltage and not used for I/O. In smaller
inputs. Approximately one in six of the
Bank 1
REF
Bank 4
Bank 0
Bank 5
pins for each bank appear in the
REF
voltage can be used within
Bank 0
Bank 5
Bank 1
Bank 4
ug002_c2_014_112900
ds031_66_112900
REF
REF
pins in
www.xilinx.com
pins
REF
devices, some V
nect within the package. These unconnected pins can be
left unconnected externally, or, if necessary, they can be
connected to V
Rules for Combining I/O Standards in the Same Bank
The following rules must be obeyed to combine different
input, output, and bi-directional standards in the same bank:
1. Combining output standards only. Output standards
2. Combining input standards only. Input standards
3. Combining input standards and output standards.
4. Combining bi-directional standards with input or
5. Additional rules for combining DCI I/O standards.
The implementation tools will enforce these design rules.
Table 5
with the same output V
combined in the same bank.
Compatible example:
Incompatible example:
with the same input V
can be combined in the same bank.
Compatible example:
Incompatible example:
Incompatible example:
Input standards and output standards with the same
input V
combined in the same bank.
Compatible example:
Incompatible example:
output standards. When combining bi-directional I/O
with other standards, make sure the bi-directional
standard can meet rules 1 through 3 above.
a. No more than one Single Termination type (input or
b. No more than one Split Termination type (input or
Virtex-II Platform FPGAs: Functional Description
summarizes all standards and voltage supplies.
SSTL2_I and LVDS_25_DCI outputs
SSTL2_I (output V
LVCMOS33 (output V
LVCMOS15 and HSTL_IV inputs
LVCMOS15 (input V
LVCMOS18 (input V
HSTL_I_DCI_18 (V
HSTL_IV_DCI_18 (V
LVDS_25 output and HSTL_I input
LVDS_25 output (output V
HSTL_I_DCI_18 input (input V
output) is allowed in the same bank.
Incompatible example:
output) is allowed in the same bank.
Incompatible example:
CCO
HSTL_IV_DCI input and HSTL_III_DCI input
HSTL_I_DCI input and HSTL_II_DCI input
CCO
and output V
CCO
to permit migration to a larger device.
pins used in larger devices do not con-
CCO
CCO
REF
CCO
CCO
CCO
REF
CCO
CCO
= 2.5V) and
= 0.9V) and
and input V
= 1.5V) and
= 1.8V) inputs
= 1.1V) inputs
CCO
requirement can be
= 3.3V) outputs
requirement can be
CCO
= 2.5V) and
= 1.8V)
REF
requirements
Module 2 of 4
6
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