XC2V40-5FGG256C Xilinx Inc, XC2V40-5FGG256C Datasheet - Page 80
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XC2V40-5FGG256C
Manufacturer Part Number
XC2V40-5FGG256C
Description
IC FPGA VIRTEX-II 40K 256-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-IIr
Datasheet
1.XC2V250-4FGG256C.pdf
(318 pages)
Specifications of XC2V40-5FGG256C
Number Of Labs/clbs
64
Total Ram Bits
73728
Number Of I /o
88
Number Of Gates
40000
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
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Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, Without DCM
Table 35: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, Without DCM
DS031-3 (v3.5) November 5, 2007
Product Specification
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
2. Output timing is measured at 50% V
LVTTL Global Clock Input to Output Delay using
Output flip-flop, 12 mA, Fast Slew Rate, without DCM.
For data output with different standards, adjust the
delays with the values shown in
Characteristics Standard Adjustments, page
Global Clock and OFF without DCM
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
R
Description
IOB Output Switching
CC
threshold with test setup shown in
14.
www.xilinx.com
Symbol
T
ICKOF
Virtex-II Platform FPGAs: DC and Switching Characteristics
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
XC2V250
XC2V500
Figure
XC2V40
XC2V80
Device
1. For other I/O standards, see
3.46
3.62
3.79
3.85
4.02
4.16
4.30
4.49
4.82
5.19
-6
Speed Grade
3.58
3.58
3.88
3.88
4.28
4.28
4.43
4.64
4.99
5.38
6.09
-5
Table
3.69
3.69
4.47
4.47
4.62
4.62
5.10
5.34
5.74
5.93
7.00
-4
Module 3 of 4
19.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
32
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