XC2V40-5FGG256C Xilinx Inc, XC2V40-5FGG256C Datasheet - Page 62
![no-image](/images/no-image-200.jpg)
XC2V40-5FGG256C
Manufacturer Part Number
XC2V40-5FGG256C
Description
IC FPGA VIRTEX-II 40K 256-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-IIr
Datasheet
1.XC2V250-4FGG256C.pdf
(318 pages)
Specifications of XC2V40-5FGG256C
Number Of Labs/clbs
64
Total Ram Bits
73728
Number Of I /o
88
Number Of Gates
40000
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
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IOB Output Switching Characteristics Standard Adjustments
Table 17
C
adjust the delays by the values shown.
Table 17: IOB Output Switching Characteristics Standard Adjustments
DS031-3 (v3.5) November 5, 2007
Product Specification
LVTTL (Low-Voltage Transistor-Transistor Logic), Slow, 2 mA
LVTTL, Slow, 4 mA
LVTTL, Slow, 6 mA
LVTTL, Slow, 8 mA
LVTTL, Slow, 12 mA
LVTTL, Slow, 16 mA
LVTTL, Slow, 24 mA
LVTTL, Fast, 2 mA
LVTTL, Fast, 4 mA
LVTTL, Fast, 6 mA
LVTTL, Fast, 8 mA
LVTTL, Fast, 12 mA
LVTTL, Fast, 16 mA
LVTTL, Fast, 24 mA
LVCMOS (Low-Voltage CMOS), 3.3V, Slow, 2 mA
LVCMOS, 3.3V, Slow, 4 mA
LVCMOS, 3.3V, Slow, 6 mA
LVCMOS, 3.3V, Slow, 8 mA
LVCMOS, 3.3V, Slow, 12 mA
LVCMOS, 3.3V, Slow, 16 mA
LVCMOS, 3.3V, Slow, 24 mA
LVCMOS, 3.3V, Fast, 2 mA
LVCMOS, 3.3V, Fast, 4 mA
LVCMOS, 3.3V, Fast, 6 mA
LVCMOS, 3.3V, Fast, 8 mA
LVCMOS, 3.3V, Fast, 12 mA
LVCMOS, 3.3V, Fast, 16 mA
LVCMOS, 3.3V, Fast, 24 mA
LVCMOS, 2.5V, Slow, 2 mA
LVCMOS, 2.5V, Slow, 4 mA
LVCMOS, 2.5V, Slow, 6 mA
LVCMOS, 2.5V, Slow, 8 mA
LVCMOS, 2.5V, Slow, 12 mA
LVCMOS, 2.5V, Slow, 16 mA
LVCMOS, 2.5V, Slow, 24 mA
LVCMOS, 2.5V, Fast, 2 mA
LVCMOS, 2.5V, Fast, 4 mA
LVCMOS, 2.5V, Fast, 6 mA
LVCMOS, 2.5V, Fast, 8 mA
LVCMOS, 2.5V, Fast, 12 mA
REF
. Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards,
gives all standard-specific adjustments for output delays terminating at pads, based on standard capacitive load,
R
Description
www.xilinx.com
LVCMOS33_S12
LVCMOS33_S16
LVCMOS33_S24
LVCMOS25_S12
LVCMOS25_S16
LVCMOS25_S24
LVCMOS33_F12
LVCMOS33_F16
LVCMOS33_F24
LVCMOS25_F12
IOSTANDARD
LVCMOS33_S2
LVCMOS33_S4
LVCMOS33_S6
LVCMOS33_S8
LVCMOS25_S2
LVCMOS25_S4
LVCMOS25_S6
LVCMOS25_S8
LVCMOS33_F2
LVCMOS33_F4
LVCMOS33_F6
LVCMOS33_F8
LVCMOS25_F2
LVCMOS25_F4
LVCMOS25_F6
LVCMOS25_F8
Virtex-II Platform FPGAs: DC and Switching Characteristics
LVTTL_S12
LVTTL_S16
LVTTL_S24
LVTTL_F12
LVTTL_F16
LVTTL_F24
LVTTL_S2
LVTTL_S4
LVTTL_S6
LVTTL_S8
Attribute
LVTTL_F2
LVTTL_F4
LVTTL_F6
LVTTL_F8
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
OLVCMOS33_S12
OLVCMOS33_S16
OLVCMOS33_S24
OLVCMOS25_S12
OLVCMOS25_S16
OLVCMOS25_S24
OLVCMOS33_F12
OLVCMOS33_F16
OLVCMOS33_F24
OLVCMOS25_F12
OLVCMOS33_S2
OLVCMOS33_S4
OLVCMOS33_S6
OLVCMOS33_S8
OLVCMOS33_F2
OLVCMOS33_F4
OLVCMOS33_F6
OLVCMOS33_F8
OLVCMOS25_S2
OLVCMOS25_S4
OLVCMOS25_S6
OLVCMOS25_S8
OLVCMOS25_F2
OLVCMOS25_F4
OLVCMOS25_F6
OLVCMOS25_F8
T
T
T
T
T
T
Parameter
T
T
T
T
T
T
T
T
OLVTTL_S12
OLVTTL_S16
OLVTTL_S24
OLVTTL_F12
OLVTTL_F16
OLVTTL_F24
OLVTTL_S2
OLVTTL_S4
OLVTTL_S6
OLVTTL_S8
OLVTTL_F2
OLVTTL_F4
OLVTTL_F6
OLVTTL_F8
Timing
–0.13
–0.22
–0.14
–0.21
9.42
5.77
4.11
2.87
2.32
1.70
1.26
6.52
2.80
1.57
0.46
0.00
7.67
4.37
3.34
2.29
1.91
1.24
1.18
5.82
2.48
1.28
0.48
0.27
9.11
5.00
4.53
3.86
2.84
2.36
2.00
4.06
1.15
0.72
0.33
0.02
-6
Speed Grade
–0.14
–0.23
–0.14
–0.21
9.71
5.95
4.24
2.96
2.39
1.75
1.30
6.72
2.88
1.62
0.48
0.00
7.91
4.50
3.44
2.36
1.97
1.27
1.22
6.00
2.55
1.31
0.49
0.28
9.39
5.16
4.67
3.98
2.93
2.43
2.06
4.18
1.18
0.74
0.34
0.02
-5
10.68
–0.15
–0.26
–0.15
–0.23
10.33
6.55
4.66
3.26
2.63
1.93
1.43
7.39
3.17
1.78
0.52
0.00
8.70
4.95
3.78
2.60
2.16
1.40
1.34
6.60
2.81
1.45
0.54
0.31
5.67
5.13
4.38
3.22
2.67
2.27
4.60
1.30
0.81
0.37
0.03
-4
Module 3 of 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14
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