EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 50

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–14
Figure 2–11. ALM in Shared Arithmetic Mode
Stratix IV Device Handbook Volume 1
datae0
datae1
datab
dataa
datad
datac
Shared Arithmetic Mode
In shared arithmetic mode, the ALM can implement a three-input add within the
ALM. In this mode, the ALM is configured with 4 four-input LUTs. Each LUT either
computes the sum of three inputs or the carry of three inputs. The output of the carry
computation is fed to the next adder (either to adder1 in the same ALM or to adder0 of
the next ALM in the LAB) using a dedicated connection called the shared arithmetic
chain. This shared arithmetic chain can significantly improve the performance of an
adder tree by reducing the number of summation stages required to implement an
adder tree.
You can find adder trees in many different applications. For example, the summation
of the partial products in a logic-based multiplier can be implemented in a tree
structure. Another example is a correlator function that can use a large adder tree to
sum filtered data samples in a given time frame to recover or de-spread data that was
transmitted using spread-spectrum technology.
Shared Arithmetic Chain
The shared arithmetic chain available in enhanced arithmetic mode allows the ALM
to implement a three-input add. This significantly reduces the resources necessary to
implement large adder trees or correlator functions.
Shared arithmetic chains can begin in either the first or sixth ALM in the LAB. The
Quartus II Compiler creates shared arithmetic chains longer than 20 (10 ALMs in
arithmetic or shared arithmetic mode) by linking LABs together automatically. For
enhanced fitting, a long shared arithmetic chain runs vertically, allowing fast
horizontal connections to the TriMatrix memory and DSP blocks. A shared arithmetic
chain can continue as far as a full column.
Figure 2–11
4-Input
4-Input
4-Input
4-Input
LUT
LUT
LUT
LUT
shared_arith_out
shows the ALM using this feature.
shared_arith_in
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
carry_out
carry_in
labclk
D
D
reg0
reg1
Q
Q
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
February 2011 Altera Corporation
Adaptive Logic Modules