EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 376
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
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- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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10–42
Table 10–10. Dedicated Configuration Pins on the Stratix IV Device (Part 1 of 4)
Stratix IV Device Handbook Volume 1
VCCPGM
VCCPD
PORSEL
nIO_PULLUP
Pin Name
User Mode
N/A
N/A
N/A
N/A
Table 10–10
properly on your board for successful configuration. Some of these pins may not be
required for your configuration schemes.
Configuration
Scheme
All
All
All
All
lists the dedicated configuration pins. You must connect these pins
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
Pin Type
Power
Power
Input
Input
Dedicated power pin. Use this pin to power all dedicated
configuration inputs, dedicated configuration outputs,
dedicated configuration bidirectional pins, and some of the
dual functional pins that are used for configuration.
You must connect this pin to 1.8, 2.5, or 3.0 V. V
ramp-up from 0 V to V
low or 4 ms when PORSEL is high. If V
up within this specified time, your Stratix IV device will not
configure successfully. If your system does not allow a
V
nCONFIG low until all power supplies are stable.
Dedicated power pin. Use this pin to power the I/O
pre-drivers, JTAG input and output pins, and design
security circuitry.
You must connect this pin to 2.5 V or 3.0 V, depending on
the I/O standards selected. For the 3.0-V I/O standard,
V
V
V
100 ms when PORSEL is low or 4 ms when PORSEL is high.
If V
Stratix IV device will not configure successfully. If your
system does not allow a V
100 ms or 4 ms, you must hold nCONFIG low until all
power supplies are stable.
Dedicated input that selects between a standard POR time
or a fast POR time. A logic low selects a standard POR time
setting of 100 ms < T
a fast POR time setting of 4 ms < T
The PORSEL input buffer is powered by V
internal 5-kΩ pull-down resistor that is always active. Tie
the PORSEL pin directly to V
Dedicated input that chooses whether the internal pull-up
resistors on the user I/O pins and dual-purpose I/O pins
(nCSO, nASDO, DATA[7..0], CLKUSR, and INIT_DONE) are
on or off before and during configuration. A logic high turns
off the weak internal pull-up resistors; a logic low turns
them on.
The nIO-PULLUP input buffer is powered by V
internal 5-kΩ pull-down resistor that is always active. The
nIO-PULLUP can be tied directly to V
pull-up resistor or tied directly to GND, depending on your
device requirements.
CCPGM
CCPD
CCPD
CCPD
CCPD
= 3.0 V. For the 2.5 V or below I/O standards,
= 2.5 V.
must ramp-up from 0 V to 2.5 V / 3.0 V within
ramp-up within 100 ms or 4 ms, you must hold
is not ramped up within this specified time, your
POR
CCPGM
Description
< 300 ms and a logic high selects
CCPD
CCPGM
within 100 ms when PORSEL is
to ramp-up time within
or GND.
April 2011 Altera Corporation
POR
CCPGM
CCPGM
Device Configuration Pins
< 12 ms.
CC
, using a 1-kΩ
and has an
is not ramped
CC
CCPGM
and has an
must
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