EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 107
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
February 2011 Altera Corporation
High-Precision Multiplier Adder Mode
Four-multiplier adder mode supports the rounding and saturation logic unit. You can
use the pipeline registers and output registers within the DSP block to pipeline the
multiplier-adder result, increasing the performance of the DSP block.
In a high-precision multiplier adder configuration, shown in
page
precision of 18 x 36 (one two-multiplier adder per half DSP block). This mode is useful
in filtering or FFT applications where a data path greater than 18 bits is required, yet
18 bits is sufficient for the coefficient precision. This can occur where the data has a
high dynamic range. If the coefficients are fixed, as in FFT and most filter applications,
the precision of 18 bits provide a dynamic range over 100 dB, if the largest coefficient
is normalized to the maximum 18-bit representation.
In these situations, the data path can be up to 36 bits, allowing sufficient capacity for
bit growth or gain changes in the signal source without loss of precision. This mode is
also extremely useful in single precision block floating point applications.
The high-precision multiplier adder is performed in two stages. The 18 × 36 multiply
is divided into two 18 × 18 multipliers. The multiplier with the LSB of the data source
is performed unsigned, while the multiplier with the MSB of the data source can be
signed or unsigned. The latter multiplier has its result left shifted by 18 bits prior to
the first adder stage, creating an effective 18 x 36 multiplier. The results of these two
adder blocks are then summed in the second stage adder block to produce the final
result:
Z[54..0] = P
where:
P
P
0
1
= A[17..0] × B[35..0]
= C[17..0] × D[35..0]
4–28, the DSP block can implement 2 two-multiplier adders, with multiplier
0
[53..0] + P
1
[53..0]
Stratix IV Device Handbook Volume 1
Figure 4–18 on
4–27
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