EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 305
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
LVDS Interface with the Use External PLL Option Enabled
Table 8–10. Signal Interface Between ALTPLL and ALTLVDS Megafunctions (Part 2 of 2)
Figure 8–21. LVDS Interface with the ALTPLL Megafunction
Note to
(1) Instantiation of pll_areset is optional for the ALTPLL instantiation.
February 2011 Altera Corporation
Parallel clock output (c2)
~(locked)
Notes to
(1) The serial clock output (c0) can only drive tx_inclock on the ALTLVDS transmitter and rx_inclock on the ALTLVDS receiver. This clock
(2) The pll_areset signal is automatically enabled for the LVDS receiver in external PLL mode. This signal does not exist for LVDS transmitter
cannot drive the core logic.
instantiation when the external PLL option is enabled.
Figure
From the ALTPLL
Table
Megafunction
8–21:
8–10:
1
The rx_syncclock port is automatically enabled in an LVDS receiver in external PLL
mode. The Quartus II compiler errors out if this port is not connected, as shown in
Figure
When generating the ALTPLL megafunction, the Left/Right PLL option is configured
to set up the PLL in LVDS mode.
ALTPLL and ALTLVDS megafunctions.
Transmitter Core Logic
Receiver Core Logic
8–21.
FPGA Fabric
tx_coreclk
rx_coreclk
Parallel clock used inside the transmitter core
logic in the FPGA fabric
To the ALTLVDS Transmitter
tx_in
rx_out
LVDS Transmitter
LVDS Receiver
(ALTLVDS)
(ALTLVDS)
—
rx_syncclock
rx_inclock
pll_areset
tx_inclock
tx_enable
rx_enable
(Note 1)
Figure 8–21
shows the connection between the
c2
locked
c0
c1
rx_syncclock (parallel clock input) and
parallel clock used inside the receiver
core logic in the FPGA fabric
pll_areset (asynchronous PLL reset
port)
ALTPLL
pll_areset
(2)
To the ALTLVDS Receiver
inclk0
Stratix IV Device Handbook Volume 1
8–27
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