EP2S180F1508C4 Altera, EP2S180F1508C4 Datasheet - Page 231

IC STRATIX II FPGA 180K 1508FBGA

EP2S180F1508C4

Manufacturer Part Number
EP2S180F1508C4
Description
IC STRATIX II FPGA 180K 1508FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S180F1508C4

Number Of Logic Elements/cells
179400
Number Of Labs/clbs
8970
Total Ram Bits
9383040
Number Of I /o
1170
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1508-FBGA
For Use With
544-1701 - DSP PRO KIT W/SII EP2S180N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1416

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Part Number
Manufacturer
Quantity
Price
Part Number:
EP2S180F1508C4
Manufacturer:
Altera
Quantity:
10 000
Part Number:
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Altera
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Part Number:
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ALTERA
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Manufacturer:
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Quantity:
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Altera Corporation
April 2011
Notes to
(1)
(2)
Number of DQS Delay Buffer Stages
Table 5–98. DQS Phase-Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR)
This error specification is the absolute maximum and minimum error. For example, skew on three delay buffer
stages in a C3 speed grade is 75 ps or ± 37.5 ps
Delay stages used for requested DQS phase shift are reported in your project’s Compilation Report in the
Quartus II software.
Table
5–98:
1
2
3
4
Notes to
(1)
(2)
Note to
(1)
Table 5–97. DQS Phase Jitter Specifications for DLL-Delayed Clock
(tDQS PHASE_JITTER)
Table 5–99. DQS Bus Clock Skew Adder Specifications
(tDQS_CLOCK_SKEW_ADDER)
Number of DQS Delay
Peak-to-peak phase jitter on the phase shifted DDS clock (digital jitter is caused
by DLL tracking).
Delay stages used for requested DQS phase shift are reported in your project’s
Compilation Report in the Quartus II software.
This skew specification is the absolute maximum and minimum skew. For
example, skew on a ×4 DQ group is 40 ps or ±20 ps.
Buffer Stages
×18 DQ per DQS
×36 DQ per DQS
×4 DQ per DQS
×9 DQ per DQS
(2)
Table
Table
Mode
–3 Speed Grade
1
2
3
4
5–99:
5–97:
.
100
25
50
75
(2)
Note (1)
–4 Speed Grade
DQS Phase Jitter
DQS Clock Skew Adder
120
30
60
90
120
30
60
90
Stratix II Device Handbook, Volume 1
40
70
75
95
DC & Switching Characteristics
–5 Speed Grade
105
140
35
70
Unit
ps
ps
ps
ps
(1)
Unit
ps
ps
ps
ps
Unit
ps
ps
ps
ps
5–95

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