EP2S180F1508C4N Altera, EP2S180F1508C4N Datasheet - Page 129

• Manufacturer Part Number: EP2S180F1508C4N
• Description: IC STRATIX II FPGA 180K 1508FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S180F1508C4N

• Number Of Logic Elements/cells: 179400
• Number Of Labs/clbs: 8970
• Total Ram Bits: 9383040
• Number Of I /o: 1170
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1508-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 179400
• # I/os (max): 1170
• Frequency (max): 711.24MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 179400
• Ram Bits: 9383040
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1508
• Package Type: FC-FBGA
• For Use With: 544-1701 - DSP PRO KIT W/SII EP2S180N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1887; EP2S180F1508C4N

Altera Corporation
May 2007
April 2006,
v4.1
December
2005, v4.0
May 2005, v3.0
January 2005,
v2.1
January 2005,
v2.0
July 2004, v1.1
February 2004,
v1.0
Table 3–7. Document Revision History (Part 2 of 2)
Document
Date and
Version
Updated “Device Security Using Configuration
Bitstream Encryption” section.
Updated “Software Interface” section.
●
●
Updated JTAG chain device limits.
Updated Table 3–3.
●
●
●
Added document to the Stratix II Device Handbook.
Updated “IEEE Std. 1149.1 JTAG Boundary-Scan
Support” section.
Updated “Operating Modes” section.
Added “Automated Single Event Upset (SEU)
Detection” section.
Updated “Device Security Using Configuration
Bitstream Encryption” section.
Updated Figure 3–2.
Changes Made
Stratix II Device Handbook, Volume 1
Summary of Changes
Configuration & Testing
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