EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 6

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

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Figure 2. Determining Reference Clock Pre-Divider Value in the Compilation Report
Figure 3. Instantiating and Connecting the pll_locked_soft_logic Module
Errata Sheet for Stratix IV GX Devices
xcvr_async_reset
top_cal_blk_clk
top_pll_inclk
system_clk
inst3
xcvr_reset_logic
xcvr_async_reset
clk
pll_locked
You can determine if the Transmitter PLL in your design uses a reference clock
pre-divider of 2, 4, or 8 by referring to the Quartus II software Compilation Report.
Figure 2
the “Resources Section” under “Fitter” in the Compilation Report. If the value in the
“Divide By” column reads 2, 4, or 8, your design is impacted by the pll_locked status
signal issue.
If the pll_locked issue impacts your design, instantiate and connect the
pll_locked_soft_logic module, as shown in
pll_locked_to_corelogic output from this module must be used in the transceiver
reset logic and any user logic that relies on the transmitter PLL lock status signal.
Click
pll_locked_soft_logic
shows an example of the “GXB Transmitter PLL” report, which you find in
pll_powerdown
tx_digitalreset
tx_datain[39..0]
to obtain the module.
pll_locked_soft_logic
serdes_io
inst2
inst
cal_blk_clk
pll_inclk
pll_powerdown[0..0]
tx_datain[39..0]
tx_digitalreset[0..0]
clk
reset
pll_locked_from_altgx
Figure
Production Devices for Stratix IV GX Devices
3. The
pll_locked_to_corelogic
tx_dataout[0..0]
pll_locked[0..0]
tx_clkout[0..0]
March 2011 Altera Corporation
top_tx_dataout