EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 2

• Manufacturer Part Number: EP4SGX360FH29C3N
• Description: IC STRATIX IV FPGA 360K 780HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX360FH29C3N

• Number Of Logic Elements/cells: 353600
• Number Of Labs/clbs: 14144
• Total Ram Bits: 22564
• Number Of I /o: 289
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Page 2
Table 1. Production Device Issues for Stratix IV GX Devices (Part 2 of 2)
Errata Sheet for Stratix IV GX Devices
“FPP Mode Configuration Failures When the Minimum Hold
Time (t
Stratix IV GX configuration fails in FPP mode when the
minimum data hold time (t
and unencrypted configuration data or 24 ns for compressed
and/or encrypted data.
“Transmitter PLL Lock (pll_locked) Status Signal”
The transmitter PLL lock status signal (pll_locked) does not
de-assert when the pll_powerdown signal is asserted in
configurations that use the reference clock pre-divider of 2, 4, or
8.
“M144K RAM Block Lock-Up”
M144K RAM blocks may lock up if there is a glitch in the clock
source.
“×8 and ×N Clock Line Timing Issue for Transceivers”
×N clock line performance limits data rates depending on clock
source configuration.
“Stratix IV GX Power-up Sequencing on Production Devices”
The device fails to power up and exit POR at low temperatures
when V
“Higher Power Supply Current During Power-Up for V
V
Higher power-up current requirements are needed for V
and V
CCA_L/R
CCA_L/R
DH
CC
”
PCI Express (PCIe) Gen2 Protocol Link Establishment Issue
) is set to 0 ns or 24 ns”
is powered after V
power supplies.
f
The PCI Express
PCIe Gen2 protocol, preventing the link from being established. When the rate switch
controller is not initialized correctly, the transmitted TS1 training sequence is
corrupted. This issue occurs intermittently and in some cases, power cycling the
device may re-establish the link. This issue affects PCIe Gen2 ×1, ×4, and ×8
configurations with and without the hard IP block. The PCIe Gen1 only
configurations are not affected.
Solution
The issue is fixed in the Quartus
recommends upgrading to the latest Quartus II software, regenerating the IP, and
recompiling your design. For complete details of the solution, refer to the
Protocol Link Solution.
Additionally, software patches are available for the Quartus II software versions
9.1 SP2 and 10.1.
To download and install the patch, refer to the
DH
CCAUX
Issue
) is set to 0 ns for uncompressed
.
®
(PCIe) rate switch controller may not be initialized correctly for the
CCPD
CCPD
and
®
II software versions 10.1 SP1 and later. Altera
All Stratix IV GX (ES and
All Stratix IV GX (ES and
All production devices
All production devices
All production devices
All production devices
production) devices
production) devices
Affected Devices
PCIe Gen2 Protocol Link
Production Devices for Stratix IV GX Devices
No plan to fix silicon. For a
soft-fix solution, refer to
“Transmitter PLL Lock
(pll_locked) Status Signal”
Refer to
Supply Current During
Power-Up for V
V
CCA_L/R
March 2011 Altera Corporation
Planned Fix
“Higher Power
” on page 21
—
—
—
—
Solution.
CCPD
PCIe Gen2
and