EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 5
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SGX360FH29C3N
Manufacturer:
Bussmann
Quantity:
40 000
Company:
Part Number:
EP4SGX360FH29C3N
Manufacturer:
ALTERA21
Quantity:
53
Production Devices for Stratix IV GX Devices
Figure 1. Reference Clock Pre-Dividers in Transmitter PLLs
March 2011 Altera Corporation
Input Reference
Clock
Transmitter PLL Lock (pll_locked) Status Signal
1
The MAX II Parallel Flash Loader drives out configuration data on the falling edge of
the DCLK. This does not affect you if you use the Max II Parallel Flash Loader as the
configuration controller.
The transmitter PLL lock status signal (pll_locked) does not de-assert when the
pll_powerdown signal is asserted in configurations that use the reference clock
pre-divider of 2, 4, or 8.
transmitter PLLs. This issue impacts the pll_locked status signal in both the CMU
PLL and the ATX PLL.
Designs that implement the recommended transceiver reset sequence described in the
Reset Control and Power Down
could potentially see a link failure after coming out of reset.
Reference Clock
Pre-Divider
/1, /2, /4, /8
Detect
PFD
Lock
Figure 1
Charge Pump
chapter in volume 2 of the Stratix IV Device Handbook
CMU/ATX PLL
Loop Filter
shows the reference clock pre-divider inside
+
/M
VCO
/L
Errata Sheet for Stratix IV GX Devices
High-Speed
CMU0
Clock
pll_locked
Page 5