EP1SGX40DF1020C7N Altera, EP1SGX40DF1020C7N Datasheet - Page 92
EP1SGX40DF1020C7N
Manufacturer Part Number
EP1SGX40DF1020C7N
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX40DF1020C7N
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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TriMatrix Memory
Figure 4–15. M512 RAM Block LAB Row Interface
4–26
Stratix GX Device Handbook, Volume 1
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
C4 and C8
Interconnects
8
Small RAM Block Local
Interconnect Region
10
M4K RAM Blocks
The M4K RAM block includes support for true dual-port RAM. The M4K
RAM block implements buffers for a wide variety of applications such as
storing processor code, implementing lookup schemes, and
implementing larger memory applications. Each block contains
4,608 RAM bits (including parity bits). M4K RAM blocks can be
configured in the following modes:
■
■
■
■
■
■
When configured as RAM or ROM, you can use an initialization file to
pre-load the memory contents.
True dual-port RAM
Simple dual-port RAM
Single-port RAM
FIFO
ROM
Shift register
2
datain
Clocks
M512 RAM
LAB Row Clocks
Block
dataout
address
Signals
Control
Altera Corporation
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
R4 and R8
Interconnects
February 2005
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