EP1SGX40DF1020C7N Altera, EP1SGX40DF1020C7N Datasheet - Page 176
EP1SGX40DF1020C7N
Manufacturer Part Number
EP1SGX40DF1020C7N
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX40DF1020C7N
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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I/O Structure
Figure 4–68. Simplified Diagram of the DQS Phase-Shift Circuitry
4–110
Stratix GX Device Handbook, Volume 1
Reference
Clock
Input
See the External Memory Interfaces chapter of the Stratix GX Device
Handbook, Volume 2 for more information on external memory interfaces.
Programmable Drive Strength
The output buffer for each Stratix GX device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL and
LVCMOS standard has several levels of drive strength that the user can
control. SSTL-3 class I and II, SSTL-2 class I and II, HSTL class I and II, and
3.3-V GTL+ support a minimum setting, the lowest drive strength that
guarantees the I
provides signal slew rate control to reduce system noise and signal
overshoot.
Comparator
Phase
Delay Chains
OH
/I
OL
of the standard. Using minimum settings
Up/Down
Counter
6
Control Signals
to DQS Pins
Altera Corporation
February 2005
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