EP1SGX40DF1020C7N Altera, EP1SGX40DF1020C7N Datasheet - Page 39
EP1SGX40DF1020C7N
Manufacturer Part Number
EP1SGX40DF1020C7N
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX40DF1020C7N
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Figure 2–24. BIST PRBS Data Path
Figure 2–25. BIST Incremental Data Path
Altera Corporation
June 2006
PRBS 8-bit
PRBS 10-bit
Table 2–9. BIST Data Output & Verifier Alignment Pattern (Part 1 of 2)
BIST Mode
Deserializer
Deserializer
Active Path
Non-active Path
Active Path
Non-active Path
Recovery
Recovery
Clock
Unit
Clock
Unit
Serializer
Serializer
2
2
8
10
Aligner
– 1
Aligner
Word
Word
– 1
Table 2–9
Channel
Output
BIST PRBS
Aligner
BIST PRBS
Channel
Aligner
Verifier
Verifier
BIST PRBS
BIST PRBS
Generator
Generator
Encoder
Encoder
8B/10B
8B/10B
shows the BIST data output and verifier alignment pattern.
Matcher
Matcher
Rate
Rate
x
x
8
10
+ x
+ x
Polynomials
7
7
+ x
+ 1
Serializer
Decoder
8B/10B
Serializer
5
Decoder
Byte
8B/10B
Byte
+ x
3
+ 1
Stratix GX Device Handbook, Volume 1
Compensation
1000000011111111
1111111111
Verifier Word Alignment Pattern
Compensation
Phase
FIFO
Deserializer
Deserializer
Phase
FIFO
Byte
Byte
Stratix GX Transceivers
Incremental
Compensation
Compensation
Incremental
Verifier
BIST
Verifier
Phase
FIFO
Phase
BIST
FIFO
Generator
Generator
BIST
BIST
2–29
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