EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 7

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

XAUI State Machine Failure—Channel 0 Shifted by One Cycle
XAUI State Machine Failure—Channel 0 Shifted by One Cycle
Figure 4. Rate Matcher FIFO Skew
Error Detection CRC Feature
February 2011 Altera Corporation
Correct Channel Alignment
XAUI Protocol Purposes
Skewed Channel 0
XAUI Protocol Purposes
Master channel for
Master channel for
Workaround
1
channel 0
channel 1
channel 2
channel 3
channel 0
channel 1
channel 2
channel 3
In XAUI functional mode, the data out of the channel 0 Rate Match FIFO may be
shifted by one byte with respect to the data of the other three channels. This causes
incorrect idle ordered set conversion, resulting in incorrect received parallel data. This
issue happens only during initialization or receiver channel reset (assertion of
rx_analogreset or rx_digitalreset).
Figure 4
A soft IP solution for this issue is available by contacting Altera.
The Error Detection CRC feature is typically used to detect single event upsets (SEU).
When enabled, the Error Detection CRC feature may cause the memory logic array
block (MLAB) RAM to operate incorrectly in Arria II GX ES devices. Only write
operations in the MLAB RAM blocks are affected.
The Error Detection CRC feature and CRC error flag operate correctly. FPGA
configuration bits are not affected by this issue.
If you do not use Error Detection CRC, no action is required. The MLAB RAM blocks
will operate correctly.
If you enable Error Detection CRC, disabling the Error Detection CRC resolves the
problem.
Also, using M9K RAM blocks or Logic Cells (LCs) instead of MLAB RAM blocks
resolves the problem.
This issue will be fixed in production devices.
K
K
K
K
--
K
K
K
shows the channel skew.
R
R
R
R
K
R
R
R
R
S
D
D
D
D
D
D
D
D
D
D
D
D
D
S
--
--
--
--
D
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
D
D
D
D
--
D
D
D
D
K
T
K
D
T
K
K
A
A
A
A
D
A
A
A
R
R
R
R
R
R
A
R
R
R
R
R
R
R
R
R
K
K
K
K
R
K
K
K
Errata Sheet for Arria II GX Devices
K = Lane Synchronization character
S = Start of packet
T = End of packet
D = Data packet
A = Alignment character
R = Clock Rate Compensation character
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