EPF10K100EFC484-1 Altera, EPF10K100EFC484-1 Datasheet - Page 30
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EPF10K100EFC484-1
Manufacturer Part Number
EPF10K100EFC484-1
Description
IC FLEX 10KE FPGA 100K 484-FBGA
Manufacturer
Altera
Series
FLEX-10KE®r
Datasheet
1.EPF10K30ETC144-3.pdf
(100 pages)
Specifications of EPF10K100EFC484-1
Number Of Logic Elements/cells
4992
Number Of Labs/clbs
624
Total Ram Bits
49152
Number Of I /o
338
Number Of Gates
257000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
FLEX 10KE
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4992
# Registers
338
# I/os (max)
338
Frequency (max)
333.33MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
4992
Ram Bits
49152
Device System Gates
257000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1935
EPF10K100EFC484-1
EPF10K100EFC484-1
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF10K100EFC484-1
Manufacturer:
UNISONIC
Quantity:
9 000
Company:
Part Number:
EPF10K100EFC484-1N
Manufacturer:
AVAGO
Quantity:
11 350
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 14. FLEX 10KE Interconnect Resources
30
I/O Element (IOE)
Row
Interconnect
Column
Interconnect
IOE
IOE
IOE
IOE
LAB
LAB
B1
A1
I/O Element
An IOE contains a bidirectional I/O buffer and a register that can be used
either as an input register for external data that requires a fast setup time,
or as an output register for data that requires fast clock-to-output
performance. In some cases, using an LE register for an input register will
result in a faster setup time than using an IOE register. IOEs can be used
as input, output, or bidirectional pins. For bidirectional registered I/O
implementation, the output register should be in the IOE, and the data
input and output enable registers should be LE registers placed adjacent
to the bidirectional pin. The Altera Compiler uses the programmable
inversion option to invert signals from the row and column interconnect
automatically where appropriate.
registers.
IOE
IOE
IOE
IOE
LAB
LAB
A2
B2
IOE
IOE
IOE
IOE
LAB
LAB
A3
B3
IOE
IOE
Figure 15
IOE
IOE
See Figure 17
shows the bidirectional I/O
for details.
Carry Chains
Cascade &
LAB A5
LAB A4
LAB B5
LAB B4
Altera Corporation
See Figure 16
for details.
IOE
IOE
IOE
IOE