EPF10K100EFC484-1 Altera, EPF10K100EFC484-1 Datasheet - Page 25

• Manufacturer Part Number: EPF10K100EFC484-1
• Description: IC FLEX 10KE FPGA 100K 484-FBGA
• Manufacturer: Altera
• Series: FLEX-10KE®r

Specifications of EPF10K100EFC484-1

• Number Of Logic Elements/cells: 4992
• Number Of Labs/clbs: 624
• Total Ram Bits: 49152
• Number Of I /o: 338
• Number Of Gates: 257000
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: FLEX 10KE
• Number Of Usable Gates: 100000
• Number Of Logic Blocks/elements: 4992
• # Registers: 338
• # I/os (max): 338
• Frequency (max): 333.33MHz
• Process Technology: CMOS
• Operating Supply Voltage (typ): 2.5V
• Logic Cells: 4992
• Ram Bits: 49152
• Device System Gates: 257000
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-1935; EPF10K100EFC484-1

Altera Corporation
Figure 12. FLEX 10KE LE Clear & Preset Modes
Asynchronous Load with Clear
Asynchronous Load with Preset
Chip-Wide Reset
Asynchronous Clear
Chip-Wide Reset
(Asynchronous
(Asynchronous
labctrl1 or
(Preset)
labctrl2
labctrl2
labctrl1
labctrl2
labctrl1
(Clear)
(Data)
(Data)
data3
data3
Load)
Load)
NOT
NOT
D
CLRN
VCC
PRN
NOT
NOT
Q
In addition to the six clear and preset modes, FLEX 10KE devices provide
a chip-wide reset pin that can reset all registers in the device. Use of this
feature is set during design entry. In any of the clear and preset modes, the
chip-wide reset overrides all other signals. Registers with asynchronous
presets may be preset when the chip-wide reset is asserted. Inversion can
be used to implement the asynchronous preset.
of how to setup the preset and clear inputs for the desired functionality.
Chip-Wide Reset
Chip-Wide Reset
Asynchronous Preset
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
labctrl1 or
labctrl2
D
CLRN
PRN
VCC
Q
D
CLRN
(Asynchronous
D
PRN
Asynchronous Load without Clear or Preset
CLRN
PRN
Q
Q
labctrl1
(Data)
Load)
data3
Chip-Wide Reset
Asynchronous Preset & Clear
Chip-Wide Reset
NOT
NOT
labctrl2
labctrl1
Figure 12
shows examples
D
CLRN
PRN
Q
D
CLRN
PRN
Q
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