EP3C120F780C8N Altera, EP3C120F780C8N Datasheet - Page 81
![IC CYCLONE III FPGA 119K 780FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP3C120F780C8N
Manufacturer Part Number
EP3C120F780C8N
Description
IC CYCLONE III FPGA 119K 780FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C120F780C8N.pdf
(274 pages)
Specifications of EP3C120F780C8N
Number Of Logic Elements/cells
119088
Number Of Labs/clbs
7443
Total Ram Bits
3981312
Number Of I /o
531
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
119088
# I/os (max)
531
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
119088
Ram Bits
3981312
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2392
544-2533
544-2533
EP3C120F780C8NES
544-2533
544-2533
EP3C120F780C8NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C120F780C8N
Manufacturer:
ALTERA
Quantity:
642
Part Number:
EP3C120F780C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Hardware Features
PLL Control Signals
© December 2009
1
1
Altera Corporation
You can use the following three signals to observe and control the PLL operation and
resynchronization.
pfdena
Use the pfdena signal to maintain the last locked frequency so that your system has
time to store its current settings before shutting down. The pfdena signal controls the
PFD output with a programmable gate. If you disable the PFD, the VCO operates at
its last set value of control voltage and frequency with some long-term drift to a lower
frequency.
areset
The areset signal is the reset or resynchronization input for each PLL. The device
input pins or internal logic can drive these input signals. When driven high, the PLL
counters reset, clearing the PLL output and placing the PLL out of lock. The VCO is
then set back to its nominal setting. When driven low again, the PLL resynchronizes
to its input as it re-locks.
You must include the areset signal in your designs if one of the following
conditions is true:
■
■
If the input clock to the PLL is toggling or unstable upon power up, assert the areset
signal after the input clock is stable and within specifications.
locked
The locked output indicates that the PLL has locked onto the reference clock and the
PLL clock outputs are operating at the desired phase and frequency set in the
Quartus II MegaWizard
Altera recommends that you use the areset and locked signals in your designs to
control and observe the status of your PLL.
This implementation is illustrated in
Figure 5–13. Locked Signal Implementation
PLL reconfiguration or clock switchover enabled in your design
Phase relationships between the PLL input clock and output clocks must be
maintained after a loss-of-lock condition
™
PLL
Plug-in Manager.
locked
Figure
V
CC
5–13.
D
OFF
Q
areset
Cyclone III Device Handbook, Volume 1
locked
5–17