EP3C120F780C8N Altera, EP3C120F780C8N Datasheet - Page 214
![IC CYCLONE III FPGA 119K 780FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP3C120F780C8N
Manufacturer Part Number
EP3C120F780C8N
Description
IC CYCLONE III FPGA 119K 780FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C120F780C8N.pdf
(274 pages)
Specifications of EP3C120F780C8N
Number Of Logic Elements/cells
119088
Number Of Labs/clbs
7443
Total Ram Bits
3981312
Number Of I /o
531
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
119088
# I/os (max)
531
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
119088
Ram Bits
3981312
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2392
544-2533
544-2533
EP3C120F780C8NES
544-2533
544-2533
EP3C120F780C8NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C120F780C8N
Manufacturer:
ALTERA
Quantity:
642
Part Number:
EP3C120F780C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
9–54
Figure 9–26. JTAG Configuration of Multiple Devices Using a Download Cable (2.5, 3.0, and 3.3-V V
Pins)
Notes to
(1) Connect these pull-up resistors to the V
(2) Connect the nCONFIG and MSEL[3..0] pins to support a non-JTAG configuration scheme. If you only use a JTAG configuration, connect the
(3) Pin 6 of the header is a V
(4) The nCE pin must be connected to ground or driven low for successful JTAG configuration.
(5) Power up the V
Cyclone III Device Handbook, Volume 1
Pin 1
10-Pin Male Header
Download Cable
nCONFIG pin to logic high and the MSEL[3..0] pins to ground. In addition, pull DCLK and DATA[0] either high or low, whichever is
convenient on your board.
MasterBlaster Serial/USB Communications Cable User
ByteBlaster II cables, this pin is connected to nCE when it is used for AS programming, otherwise it is a no connect.
to 2.5 V. Pin 4 of the header is a V
circuit boards, DC power supply, or 5.0 V from the USB cable. For this value, refer to the
Figure
V
CCA
(5)
10 kΩ
VIO
(3)
9–26:
1 kΩ
V
CC
CCA
of the ByteBlaster II, USB-Blaster, or ByteBlasterMV cable with a 2.5- V supply from V
V
CCA
10 kΩ
IO
(2)
(2)
(2)
(2)
(2)
reference voltage for the MasterBlaster output driver. V
V
CCIO
10
CC
(1)
DCLK
nST A TUS
DATA[0]
nCONFIG
MSEL[3..0]
nCEO
nCE
TDI
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
kΩ
power supply for the MasterBlaster cable. The MasterBlaster cable can receive power from either 5.0- or 3.3-V
TMS
(4)
Cyclone III Device
CCIO
Family
TCK
CONF_DONE
supply of the bank in which the pin resides.
TDO
V
Guide. In the ByteBlasterMV cable, this pin is a no connect. In the USB-Blaster and
CCIO
10
(1)
kΩ
(2)
(2)
(2)
(2)
(2)
V
CCIO
10
(1)
nST A TUS
DATA[0]
DCLK
nCONFIG
MSEL[3..0]
nCEO
nCE
TDI
kΩ
TMS
Cyclone III Device
(4)
IO
Family
must match the V
CONF_DONE
TCK
MasterBlaster Serial/USB Communications User
TDO
V
CCIO
10
CCA
CCA
(1)
kΩ
of the device. For this value, refer to the
. Third-party programmers must switch
© December 2009 Altera Corporation
(2)
(2)
(2)
(2)
(2)
V
CCIO
10
(1)
nST A TUS
DATA[0]
DCLK
nCONFIG
MSEL[3..0]
nCEO
nCE
TDI
CCIO
kΩ
TMS
(4)
Powering the JTAG
Cyclone III Device
Configuration Features
Family
TCK
CONF_DONE
TDO
V
CCIO
Guide.
10
(1)
kΩ