EP3C120F780C8N Altera, EP3C120F780C8N Datasheet - Page 195
![IC CYCLONE III FPGA 119K 780FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP3C120F780C8N
Manufacturer Part Number
EP3C120F780C8N
Description
IC CYCLONE III FPGA 119K 780FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C120F780C8N.pdf
(274 pages)
Specifications of EP3C120F780C8N
Number Of Logic Elements/cells
119088
Number Of Labs/clbs
7443
Total Ram Bits
3981312
Number Of I /o
531
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
119088
# I/os (max)
531
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
119088
Ram Bits
3981312
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2392
544-2533
544-2533
EP3C120F780C8NES
544-2533
544-2533
EP3C120F780C8NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C120F780C8N
Manufacturer:
ALTERA
Quantity:
642
Part Number:
EP3C120F780C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
© December 2009
1
Altera Corporation
PS Configuration Using an External Host
In the PS configuration scheme, you can use an intelligent host such as MAX II or
microprocessor that controls the transfer of configuration data from a storage device,
such as flash memory, to the target Cyclone III device family. You can store the
configuration data in .rbf, .hex, or .ttf format.
Figure 9–14
device family and an external host device for a single-device configuration.
Figure 9–14. Single-Device PS Configuration Using an External Host
Notes to
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the device. V
(2) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0],
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[0] and DCLK must fit the maximum overshoot
To begin configuration, the external host device must generate a low-to-high
transition on the nCONFIG pin. When nSTATUS is pulled high, the external host
device must place the configuration data one bit at a time on the DATA[0]pin. If you
are using configuration data in a .rbf, .ttf, or .hex file, you must first send the LSB of
each data byte. For example, if the .rbf contains the byte sequence 02 1B EE 01 FA, the
serial bitstream you must send to the device is:
Cyclone III device family receives configuration data on the DATA[0]pin and the
clock is received on the DCLK pin. Data is latched into the device on the rising edge of
DCLK. Data is continuously clocked into the target device until CONF_DONE goes high
and the device enters the initialization state.
Two DCLK falling edges are required after CONF_DONE goes high to begin device
initialization.
The INIT_DONE pin is released and pulled high when initialization is complete. The
external host device must be able to detect this low-to-high transition which signals
the device has entered user mode. When initialization is complete, the device enters
user mode. In user mode, the user I/O pins no longer have weak pull-up resistors and
function as assigned in your design.
enough to meet the V
refer to
equation outlined in
Figure
0100-0000 1101-1000 0111-0111 1000-0000 0101-1111
Table 9–7 on page
shows the configuration interface connections between a Cyclone III
9–14:
“Configuration and JTAG Pin I/O Requirements” on page
IH
(MAX II Device or
Microprocessor)
External Host
specification of the I/O on the device and the external host.
9–11. Connect the MSEL pins directly to V
ADDR
Memory
DATA[0]
10 kΩ
V CCIO (1) V CCIO (1)
10 kΩ
GND
CONF_DONE
nSTATUS
nCE
DATA[0] (4)
nCONFIG
DCLK (4)
Cyclone III
Device Family
MSEL[3..0]
CCA
or ground.
nCEO
Cyclone III Device Handbook, Volume 1
9–7.
N.C. (2)
(3)
CC
must be high
9–35