EP1S10F780C6 Altera, EP1S10F780C6 Datasheet - Page 93
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EP1S10F780C6
Manufacturer Part Number
EP1S10F780C6
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F780C6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1111
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F780C6
Manufacturer:
FC
Quantity:
34
Company:
Part Number:
EP1S10F780C6
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S10F780C6
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP1S10F780C6ES
Manufacturer:
ALTERA
Quantity:
38
Company:
Part Number:
EP1S10F780C6ES
Manufacturer:
ALTERA
Quantity:
44
Figure 2–46. Regional Clock Bus
Altera Corporation
July 2005
Fast Regional Clock Network [1..0]
Regional Clock Network [3..0]
Global Clock Network [15..0]
IOE clocks have horizontal and vertical block regions that are clocked by
eight I/O clock signals chosen from the 22 quadrant or half-quadrant
clock resources.
quadrant relationship to the I/O clock regions, respectively. The vertical
regions (column pins) have less clock delay than the horizontal regions
(row pins).
Figures 2–47
or Half-Quadrant
Clocks Available
to a Quadrant
Clock [21..0]
and
2–48
show the quadrant and half-
Stratix Device Handbook, Volume 1
Vertical I/O Cell
IO_CLK[7..0]
Lab Row Clock [7..0]
Horizontal I/O
Cell IO_CLK[7..0]
Stratix Architecture
2–79