EP1S10F780C6 Altera, EP1S10F780C6 Datasheet - Page 106
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EP1S10F780C6
Manufacturer Part Number
EP1S10F780C6
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F780C6
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1111
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PLLs & Clock Networks
2–92
Stratix Device Handbook, Volume 1
bandwidth is tuned by varying the charge pump current, loop filter
resistor value, high frequency capacitor value, and m counter value. You
can manually adjust these values if desired. Bandwidth is programmable
from 200 kHz to 1.5 MHz.
External Clock Outputs
Enhanced PLLs 5 and 6 each support up to eight single-ended clock
outputs (or four differential pairs). Differential SSTL and HSTL outputs
are implemented using 2 single-ended output buffers which are
programmed to have opposite polarity. In Quartus II software, simply
assign the appropriate differential I/O standard and the software will
implement the inversion. See
Figure
2–55.
Altera Corporation
July 2005