EPF10K100ABC356-3 Altera, EPF10K100ABC356-3 Datasheet - Page 39
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EPF10K100ABC356-3
Manufacturer Part Number
EPF10K100ABC356-3
Description
IC FLEX 10KA FPGA 100K 356-BGA
Manufacturer
Altera
Series
FLEX-10K®r
Datasheet
1.EPF10K10ATC100-3.pdf
(128 pages)
Specifications of EPF10K100ABC356-3
Number Of Logic Elements/cells
624
Number Of Labs/clbs
624
Total Ram Bits
24576
Number Of I /o
274
Number Of Gates
158000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
356-BGA
Family Name
FLEX 10KA
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4992
# Registers
1218
# I/os (max)
274
Frequency (max)
125MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
3.3V
Logic Cells
4992
Ram Bits
24567
Device System Gates
158000
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
356
Package Type
BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-2191
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF10K100ABC356-3
Manufacturer:
ALTERA
Quantity:
36
Company:
Part Number:
EPF10K100ABC356-3
Manufacturer:
MAXIM
Quantity:
304
Company:
Part Number:
EPF10K100ABC356-3N
Manufacturer:
ALTERA
Quantity:
1 259
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Slew-Rate Control
The output buffer in each IOE has an adjustable output slew rate that can
be configured for low-noise or high-speed performance. A slower slew
rate reduces system noise and adds a maximum delay of approximately
2.9 ns. The fast slew rate should be used for speed-critical outputs in
systems that are adequately protected against noise. Designers can specify
the slew rate on a pin-by-pin basis during design entry or assign a default
slew rate to all pins on a device-wide basis. The slow slew rate setting
affects only the falling edge of the output.
Open-Drain Output Option
FLEX 10K devices provide an optional open-drain (electrically equivalent
to an open-collector) output for each I/O pin. This open-drain output
enables the device to provide system-level control signals (e.g., interrupt
and write enable signals) that can be asserted by any of several devices. It
can also provide an additional wired-OR plane. Additionally, the Altera
software can convert tri-state buffers with grounded data inputs to open-
drain pins automatically.
Open-drain output pins on FLEX 10K devices (with a pull-up resistor to
the 5.0-V supply) can drive 5.0-V CMOS input pins that require a V
of
IH
3.5 V. When the open-drain pin is active, it will drive low. When the pin is
inactive, the trace will be pulled up to 5.0 V by the resistor. The open-drain
pin will only drive low or tri-state; it will never drive high. The rise time
is dependent on the value of the pull-up resistor and load impedance. The
I
current specification should be considered when selecting a pull-up
OL
resistor.
Output pins on 5.0-V FLEX 10K devices with V
= 3.3 V or 5.0 V (with
CCIO
a pull-up resistor to the 5.0-V supply) can also drive 5.0-V CMOS input
pins. In this case, the pull-up transistor will turn off when the pin voltage
exceeds 3.3 V. Therefore, the pin does not have to be open-drain.
MultiVolt I/O Interface
The FLEX 10K device architecture supports the MultiVolt I/O interface
feature, which allows FLEX 10K devices to interface with systems of
differing supply voltages. These devices have one set of V
pins for
CC
internal operation and input buffers (VCCINT) and another set for I/O
output drivers (VCCIO).
Altera Corporation
39