EPF10K100ABC356-3 Altera, EPF10K100ABC356-3 Datasheet - Page 24
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EPF10K100ABC356-3
Manufacturer Part Number
EPF10K100ABC356-3
Description
IC FLEX 10KA FPGA 100K 356-BGA
Manufacturer
Altera
Series
FLEX-10K®r
Datasheet
1.EPF10K10ATC100-3.pdf
(128 pages)
Specifications of EPF10K100ABC356-3
Number Of Logic Elements/cells
624
Number Of Labs/clbs
624
Total Ram Bits
24576
Number Of I /o
274
Number Of Gates
158000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
356-BGA
Family Name
FLEX 10KA
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4992
# Registers
1218
# I/os (max)
274
Frequency (max)
125MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
3.3V
Logic Cells
4992
Ram Bits
24567
Device System Gates
158000
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
356
Package Type
BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-2191
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF10K100ABC356-3
Manufacturer:
ALTERA
Quantity:
36
Company:
Part Number:
EPF10K100ABC356-3
Manufacturer:
MAXIM
Quantity:
304
Company:
Part Number:
EPF10K100ABC356-3N
Manufacturer:
ALTERA
Quantity:
1 259
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Asynchronous Preset
An asynchronous preset is implemented as either an asynchronous load,
or with an asynchronous clear. If DATA3 is tied to V
, asserting
CC
LABCTRL1 asynchronously loads a one into the register. Alternatively, the
Altera software can provide preset control by using the clear and
inverting the input and output of the register. Inversion control is
available for the inputs to both LEs and IOEs. Therefore, if a register is
preset by only one of the two LABCTRL signals, the DATA3 input is not
needed and can be used for one of the LE operating modes.
Asynchronous Preset & Clear
When implementing asynchronous clear and preset, LABCTRL1 controls
the preset and LABCTRL2 controls the clear. DATA3 is tied to V
,
CC
therefore, asserting LABCTRL1 asynchronously loads a one into the
register, effectively presetting the register. Asserting LABCTRL2 clears the
register.
Asynchronous Load with Clear
When implementing an asynchronous load in conjunction with the clear,
LABCTRL1 implements the asynchronous load of DATA3 by controlling
the register preset and clear. LABCTRL2 implements the clear by
controlling the register clear; LABCTRL2 does not have to feed the preset
circuits.
Asynchronous Load with Preset
When implementing an asynchronous load in conjunction with preset, the
Altera software provides preset control by using the clear and inverting
the input and output of the register. Asserting LABCTRL2 presets the
register, while asserting LABCTRL1 loads the register. The Altera software
inverts the signal that drives DATA3 to account for the inversion of the
register’s output.
Asynchronous Load without Preset or Clear
When implementing an asynchronous load without preset or clear,
LABCTRL1 implements the asynchronous load of DATA3 by controlling
the register preset and clear.
24
Altera Corporation