EPF10K100ABC356-3 Altera, EPF10K100ABC356-3 Datasheet - Page 23
![IC FLEX 10KA FPGA 100K 356-BGA](/photos/6/73/67387/544-356-bga_sml.jpg)
EPF10K100ABC356-3
Manufacturer Part Number
EPF10K100ABC356-3
Description
IC FLEX 10KA FPGA 100K 356-BGA
Manufacturer
Altera
Series
FLEX-10K®r
Datasheet
1.EPF10K10ATC100-3.pdf
(128 pages)
Specifications of EPF10K100ABC356-3
Number Of Logic Elements/cells
624
Number Of Labs/clbs
624
Total Ram Bits
24576
Number Of I /o
274
Number Of Gates
158000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
356-BGA
Family Name
FLEX 10KA
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4992
# Registers
1218
# I/os (max)
274
Frequency (max)
125MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
3.3V
Logic Cells
4992
Ram Bits
24567
Device System Gates
158000
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
356
Package Type
BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-2191
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF10K100ABC356-3
Manufacturer:
ALTERA
Quantity:
36
Company:
Part Number:
EPF10K100ABC356-3
Manufacturer:
MAXIM
Quantity:
304
Company:
Part Number:
EPF10K100ABC356-3N
Manufacturer:
ALTERA
Quantity:
1 259
Altera Corporation
Figure 10. LE Clear & Preset Modes
Chip-Wide Reset
Chip-Wide Reset
Asynchronous Clear
(Asynchronous
(Asynchronous
Asynchronous Load with Clear
Asynchronous Load with Preset
labctrl1 or
(Preset)
labctrl2
labctrl2
labctrl2
labctrl1
labctrl1
(Clear)
(Data)
(Data)
data3
data3
Load)
Load)
NOT
NOT
D
CLRN
VCC
PRN
NOT
NOT
Q
Asynchronous Clear
The flipflop can be cleared by either LABCTRL1 or LABCTRL2. In this
mode, the preset signal is tied to V
Chip-Wide Reset
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Chip-Wide Reset
Asynchronous Preset
labctrl1 or
labctrl2
D
CLRN
PRN
Q
VCC
D
CLRN
PRN
D
CLRN
PRN
(Asynchronous
Q
Asynchronous Load without Clear or Preset
Q
CC
labctrl1
(Data)
Load)
data3
to deactivate it.
Chip-Wide Reset
Chip-Wide Reset
NOT
NOT
Asynchronous Clear & Preset
labctrl1
labctrl2
D
CLRN
PRN
D
CLRN
PRN
Q
Q
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