EP1S10F672C7 Altera, EP1S10F672C7 Datasheet - Page 79

• Manufacturer Part Number: EP1S10F672C7
• Description: IC STRATIX FPGA 10K LE 672-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F672C7

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 345
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 345
• Frequency (max): 420.17MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1109

Figure 2–35. Simple Multiplier Mode
Note to
(1)
Altera Corporation
July 2005
Data B
Data A
These signals are not registered or registered once to match the data path pipeline.
Figure
shiftout B
2–35:
shiftin B
shiftout A
ENA
ENA
D
D
CLRN
CLRN
DSP blocks can also implement one 36 × 36-bit multiplier in multiplier
mode. DSP blocks use four 18 × 18-bit multipliers combined with
dedicated adder and internal shift circuitry to achieve 36-bit
multiplication. The input shift register feature is not available for the
36 × 36-bit multiplier. In 36 × 36-bit mode, the device can use the register
that is normally a multiplier-result-output register as a pipeline stage for
the 36 × 36-bit multiplier.
mode.
shiftin A
signa (1)
signb (1)
Q
Q
clock
ena
aclr
ENA
D
Figure 2–36
CLRN
Q
shows the 36 × 36-bit multiply
Stratix Device Handbook, Volume 1
ENA
D
CLRN
Q
Stratix Architecture
Data Out
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