EP3C40F780I7 Altera, EP3C40F780I7 Datasheet - Page 72

• Manufacturer Part Number: EP3C40F780I7
• Description: IC CYCLONE III FPGA 40K 780 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C40F780I7

• Number Of Logic Elements/cells: 39600
• Number Of Labs/clbs: 2475
• Total Ram Bits: 1161216
• Number Of I /o: 535
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 39600
• # I/os (max): 535
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 39600
• Ram Bits: 1161216
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

5–8
clkena Signals
Figure 5–5. clkena Implementation: Output Enable
Cyclone III Device Handbook, Volume 1
clkin
clkena
clk_out
1
1
The Cyclone III device family supports clkena signals at the GCLK network level.
This allows you to gate-off the clock even when a PLL is used. Upon re-enabling the
output clock, the PLL does not need a resynchronization or re-lock period because the
circuit gates off the clock at the clock network level. In addition, the PLL can remain
locked independent of the clkena signals because the loop-related counters are not
affected.
Figure 5–4
Figure 5–4. clkena Implementation
The clkena circuitry controlling the output C0 of the PLL to an output pin is
implemented with two registers instead of a single register, as shown in
Figure 5–5
signal is sampled on the falling edge of the clock (clkin).
This feature is useful for applications that require low power or sleep mode.
The clkena signal can also disable clock outputs if the system is not tolerant to
frequency overshoot during PLL resynchronization.
shows how to implement the clkena signal.
shows the waveform example for a clock output enable. The clkena
clkena
clkin
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
D
Q
clkena_out
© December 2009 Altera Corporation
clk_out
Figure
Clock Networks
5–4.